L14-4up

L14-4up - Building the Beta I wonder where this goes? CPU...

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L14 – Building a Beta 1 6.004 – Fal 2010 10/26/10 Building the Beta I wonder where this goes? Lab #5 due Thursday! L14 – Building a Beta 2 6.004 – Fal 2010 10/26/10 CPU Design Tradeo f s Minimum Cost : measured by the size of the circuit. 0 1 0 1 Best Performance/Price: measured by the ratio of MIPS to size. In power-sensitive applications MIPS/Wa ± is important too. Maximum Performance: measured by the numbers of instructions executed per second L14 – Building a Beta 3 6.004 – Fal 2010 10/26/10 Performance Measure MIPS = Clock Frequency (MHz) C.P.I. Millions of Instructions per Second Clocks per instruction PUSHING PERFORMANCE . .. TODAY: 1 cycle/inst. LATER: more MHz via pipelining L14 – Building a Beta 4 6.004 – Fal 2010 10/26/10 The Beta ISA Instruction classes distinguished by OPCODE: OP OPC MEM Transfer of Control OpCode 6 Operate class: Reg[Rc] ! Reg[Ra] op Reg[Rb] 6 5 5 5 11 Ra Rc Rb (UNUSED) 0 1 X X X X Operate class: Reg[Rc] ! Reg[Ra] op SXT(C) 16 Ra Rc Literal C (signed) 1 1 X X X X Opcodes, both formats: ADD SUB MUL* DIV* *optional CMPEQ CMPLE CMPLT AND OR XOR SHL SHR SRA LD: Reg[Rc] ! Mem[Reg[Ra]+SXT(C)] ST: Mem[Reg[Ra]+SXT(C)] ! Reg[Rc] JMP: Reg[Rc] ! PC+4; PC ! Reg[Ra] BEQ: Reg[Rc] ! PC+4; if Reg[Ra]=0 then PC ! PC+4+4*SXT(C) BNE: LDR: Reg[Rc] ! Mem[PC + 4 + 4*SXT(C)] Reg[Rc] ! PC+4; if Reg[Ra] " 0 then PC ! PC+4+4*SXT(C) Ra Rc Literal C (signed) 1 0 X X X X
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L14 – Building a Beta 5 6.004 – Fal 2010 10/26/10 Approach: Incremental Featurism Each instruction class can be implemented using a simple component repertoire. We’ll try implementing data paths for each class individually, and merge them (using MUXes, etc). Steps: 1. Operate instructions 2. Load & Store Instructions 3. Jump & Branch instructions 4. Exceptions 5. Merge data paths Our Bag of Components: Registers 0 1 Muxes ALU A B “Black box” ALU Data Memory WD A RD R/W Register File (3-port) RA1 RA2 WA WE WD RD1 RD2 Instruction Memory A D Memories L14 – Building a Beta 6 6.004 – Fal 2010 10/26/10 D Q 1 0 s Q D EN clk Multi-Port Register Files Register File (3-port) RA1 RA2 WA WE WD RD1 RD2 5 32 CLK Write Enable Write Address Write Data (independent Read addresses) (Independent Read Data) 32 32 2 combinational READ ports*, 1 clocked WRITE port *internal logic ensures Reg[31] reads as 0 5 5 dest asel bsel EN EN EN EN clk Read Port A Read Port B Write Port L14 – Building a Beta 7 6.004 – Fal 2010 10/26/10 Register File Timing CLK WE WA WD RA RD A Reg[A] A new Reg[A] 2 combinational READ ports, 1 clocked WRITE port What if (say) WA=RA1???
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L14-4up - Building the Beta I wonder where this goes? CPU...

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