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L21-4up - Pipelining the Beta bet!ta'be-t n Any of various...

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L21 – Pipelining the Beta 1 6.004 – Fal 2010 11/23/10 Pipelining the Beta bet ! ta ('be-t&) n. Any of various species of small, brightly colored, long-finned freshwater fishes of the genus Betta, found in southeast Asia. be ! ta ( b b A- t&, b b E -) n. 1. The second letter of the Greek alphabet. 2. The exemplary computer system used in 6.004. I don t think they mean the fsh. .. maybe they ll give me partial credit. .. Lab #8 meeting deadline is next Thursday L21 – Pipelining the Beta 2 6.004 – Fal 2010 11/23/10 CPU PerFormance We ve got a working Beta… can we make it fast? MIPS = Millions oF Instructions/Second ±req = Clock ±requency, MHz CPI = Clocks per Instruction MIPS = Freq CPI To Increase MIPS: 1. DECREASE CPI. - RISC simplicity reduces CPI to 1.0. - CPI below 1.0? Tough. .. You ll see multiple instruction issue machines in 6.823. 2. INCREASE ±req. - ±req limited by delay along longest combinational path; hence - PIPELINING is the key to improved perFormance through Fast clocks. L21 – Pipelining the Beta 3 6.004 – Fal 2010 11/23/10 Beta Timing New PC PC+4 ±etch Inst. Control Logic Read Regs RA2SEL mux ASEL mux BSEL mux ALU ±etch data +O±±SET WDSEL mux R± setup PC setup Mem setup PCSEL mux =0? CLK ! CLK ! Wanted: longest paths Complications: some apparent paths aren t l possible z operations have variable execution times (eg, ALU) time axis is not to scale (eg, t PD,MEM is very big!) l precedence graph z PC+4 +O±±SET LD(R1,10,R0) LDR(X,R3) L21 – Pipelining the Beta 4 6.004 – Fal 2010 11/23/10 Why isn t this a 20-minute lecture? 1. The Beta isn t combinational… ! Explicit state in register fle, memory; ! Hidden state in PC. 2. Consecutive operations – instruction executions – interact: Jumps, branches dynamically change instruction sequence Communication through registers, memory Our goals: Move slow components into separate pipeline stages, running clock Faster Maintain instruction semantics oF unpipelined Beta as Far as possible We ve learned how to pipeline combinational circuits. What s the big deal?
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L21 – Pipelining the Beta 5 6.004 – Fal 2010 11/23/10 Ultimate Goal: 5-Stage Pipeline GOAL: Maintain (nearly) 1.0 CPI, but increase clock speed to barely include slowest components (mems, regfle, ALU) APPROACH: structure processor as 5-stage pipeline: IF Instruction Fetch stage : Maintains PC, ±etches one instruction per cycle and passes it to WB Write-Back stage : writes result back into register fle. RF Register File stage : Reads source operands ±rom register fle, passes them to ALU ALU stage : Per±orms indicated operation, passes result to MEM Memory stage : I± it s a LD, use ALU result as an address, pass mem data (or ALU result i± not LD) to L21 – Pipelining the Beta 6 6.004 – Fal 2010 11/23/10 First Steps: A Simple 2-Stage Pipeline ASEL 0 1 Data Memory RD WD Adr R/W W D S E L 0 1 2 <25:21> 0 1 XP
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L21-4up - Pipelining the Beta bet!ta'be-t n Any of various...

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