L22-4up

L22-4up - Pipeline Issues This pipeline stu makes my head...

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L22 – Pipeline Issues 1 6.004 – Fal 2010 11/30/10 Pipeline Issues This pipeline stu f makes my head hurt! Maybe it’s that dumb hat Labs #7 and #8 meeting due Thursday, Quiz #4 on Friday! L22 – Pipeline Issues 2 6.004 – Fal 2010 11/30/10 Recalling Data Hazards IF RF ALU WB i i+1 i+2 i+3 i+4 i+5 i+6 ADD CMP MUL SUB ADD CMP MUL SUB ADD CMP MUL SUB ADD CMP MUL SUB ADD(r1, r2, r3) CMPLEC(r3, 100, r0) MULC(r3, 100, r4) SUB(r0, r4, r5) PROBLEM: Subsequent instructions can reference the contents of a register well before the pipeline stage where the register is wri ± en. SOLUTION #2: Add special hardware to maintain the sequential execution semantics of the ISA. SOLUTION #1: Deal with it in SOFTWARE; expose the pipeline for all to see. L22 – Pipeline Issues 3 6.004 – Fal 2010 11/30/10 Bypass Paths Register File WA WD WE ALU A B Y IR WB IR ALU Register File RA1 RA2 RD1 RD2 IR RF Y WB B A Bypass muxes MULC(r3,100,r4) SUB(r0,r4,r5) CMPLEC(r3,100,r0) Add special data paths, called BYPASSES, that route the results of the ALU and WB stages to the RF stage, thus substituting the register’s old contents with a value that will be wri ± en to that register at some point in the future. Detection of these cases has to be incorporated into the decoding logic of the RF stage, which basically looks at the instructions in the ALU and WB stage to see if their destination register matches a source register reference. IF RF ALU WB But there are some problems that BYPASSING CAN’T FIX! L22 – Pipeline Issues 4 6.004 – Fal 2010 11/30/10 Load Hazards Consider LOADS: Can we ±x all these problems using bypass paths? IF RF ALU WB i i+1 i+2 i+3 i+4 i+5 i+6 LD ADD XOR LD ADD XOR LD ADD XOR LD ADD XOR LD(r1, 0, r4) ADD(r4, r1, r5) XOR(r3, r4, r6) The hazard between the XOR and the LD can be addressed by our established bypass paths…
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L22 – Pipeline Issues 5 6.004 – Fal 2010 11/30/10 Load Hazard (easy) (NB: SAME RF AS ABOVE!) +4 PC RF PC MEM PC ALU Rb: <15:11> Ra <20:16> RA2SEL Rc <25:21> Instruction Memory A D IR RF Instruction Fetch + C: <15:0> << 2 sign-extended Register File WA WD WE WDSEL 0 1 2 IR MEM D MEM Y MEM D ALU B IR ALU A 0 1 BSEL Z ALU A B Y Data Memory WD Adr R/W Register File ALU Write Back ASEL 0 1 <PC>+C PCSEL JT 0 1 2 3 4 XAdr ILL OP PC IF 00 1 XP WASEL Register File RA1 RA2 RD1 RD2 JT C: <15:0> sign-extended ALUFN WERF XOR(r3, r4, r6) LD(r1, 0, r4) The XOR operand r4 can simply be bypassed from the output of the memory in the WB stage to the RF stage… by our normal bypass path. L22 – Pipeline Issues 6 6.004 – Fal 2010 11/30/10 Structural Data Hazard The XOR hazard is pre ± y easy, but… IF RF ALU WB i i+1 i+2 i+3 i+4 i+5 i+6 LD ADD XOR LD ADD XOR LD ADD XOR LD ADD XOR LD(r1, 0, r4) ADD(r1, r4, r5) XOR(r3, r4, r6) ??? How do we ±x this one? In a 4-stage pipeline, for a LD instruction fetched during clock i, the data from memory isn’t returned from memory until late into cycle i+3.
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L22-4up - Pipeline Issues This pipeline stu makes my head...

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