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Unformatted text preview: L23 – Communication 1 6.004 – Fal 2010 12/2/10 Interconnect & Communication What is the big deal with these things? I don ’ t see what is so exciting about the l back-side z either. Space, Time, & stu ff … Lab #7 and #8 checko ff s due tonight Quiz #4 tomorrow L23 – Communication 2 6.004 – Fal 2010 12/2/10 Computer System Technologies What ’ s the most important part of this picture? Mother boards SDRAM LAN technology Linux Windows XP Hard Disk Drives DRAM Flash Memory Graphics Acceleration ActiveX Controls App Servers L23 – Communication 3 6.004 – Fal 2010 12/2/10 Technology comes & goes; interfaces last forever Interfaces typically deserve more engineering a ention than the technologies they interface… • Abstraction: should outlast many technology generations • Often l virtualized z to extend beyond original function (e.g. memory, I/O, services, machines) • Represent more potential value to their proprietors than the technologies they connect. Interface sob stories: • Interface l warts z : Windows l aux.c z bug, Big/li le Endian wars • IBM PC debacle ... and many success stories: • IBM 360 Instruction set architecture; Postscript; Compact Flash; ... • Backplane buses L23 – Communication 4 6.004 – Fal 2010 12/2/10 CPU MEM I/O DISK I/O MEM Ancient Times (Ad hoc connections) System Interfaces & Modularity Late 60s (Processor-dependent Bus) CPU MEM I/O DISK I/O MEM ? 80s (Processor-independent Bus) CPU CPU I/O DISK I/O MEM Today Buses Galore MEM MEM CPU DISK I/O I/O L2/L3 $ Graphics I/O PCIe lanes Front-side bus Back-side bus Bridge L23 – Communication 5 6.004 – Fal 2010 12/2/10 Interface Standard: Backplane Bus MODULE LOGIC a data operation start finish clock address d BUS LINES Printed Circuit Cards Modular cards that plug into a common backplane: CPUs Memories Bulk storage I/O devices S/W? The backplane provides: Power Common system clock Wires for communication L23 – Communication 6 6.004 – Fal 2010 12/2/10 Synchronous Bus Clock Timing CLK Signal at source assertion edge sample edge Signal at destination Allow for several l round-trip z bus delays so that ringing can die down. l Se ling Time z l de-skew time z L23 – Communication 7 6.004 – Fal 2010 12/2/10 A Simple Bus Transaction CLK assertion edge sample edge start finish operation address data WRITE (Master) (Master) (Master) (Master) (Slave) MASTER: 1) Chooses bus operation 2) Asserts an address 3) Waits for a slave to answer....
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- Network topology, Computer buses, Interconnect & Communication