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- 1 - Lab #2 M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.004 Computation Structures Lab #2 Your mission this week is to design and test a CMOS circuit that performs addition on two unsigned 4-bit numbers, producing a 5-bit result: A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 S4 ADD When you’ve completed and tested your design, you can ask JSim to send your circuit to the on- line assignment system using the process described at the end of Lab #1. The checkoff file for Lab #2 (lab2checkoff.jsim) checks that your circuit has the right functionality; the on-line system will give you 5 points for checking off your lab using this file. (You’ll receive your points after completing the on-line questions and a checkoff meeting with a TA.) Note: Our ability to provide automated checkoffs is predicated on trusting that you’ll use the checkoff and library files as given. Since these files are included in your submission, we will be checking to see if these files have been used as intended. Submittals that include modified checkoff or library files will be regarded as a serious breach of our trust and will be dealt with accordingly. Some suggestions on how to proceed: Å Let’s start with a simple ripple-carry adder based on the full-adder module discussed in lecture. Later we’ll discuss higher performance adder architectures you can use in the implementation of the Beta (the computer central processing unit we’ll be designing in later labs). The full adder module has 3 inputs (A, B and C i ) and 2 outputs (S and C o ). The logic equations and truth table for S and C o are shown below. in
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This document was uploaded on 03/07/2011.

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