lab3

lab3 - MASSACHUSETTS INSTITUTE OF TECHNOLOGY DEPARTMENT OF...

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6.004 Computation Structures - 1 - Lab #3 M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.004 Computation Structures Lab #3 In this laboratory exercise, we’ll build the arithmetic and logic unit (ALU) for the Beta processor. The ALU has two 32-bit inputs (which we’ll call “A” and “B”) and produces one 32-bit output. We’ll start by designing each piece of the ALU as a separate circuit, each producing its own 32- bit output. Then we’ll combine these outputs into a single ALU result. When designing circuitry there are three separate factors that can be optimized: (1) design for maximum performance (minimum latency) (2) design for minimum cost (minimum area) (3) design for the best cost/performance ratio (minimize area*latency) Happily it’s often possible to do all three at once but in some portions of the circuit some sort of design tradeoff will need to be made. When designing your circuitry you should choose which of these three factors is most important to you and optimize your design accordingly. A functional ALU design will earn six points. Four additional points can be earned if you implement the optional multiplier unit – see the section labeled “Optional Design Problem: Implementing Multiply” for details. Standard Cell Library The building blocks for our design will be a family of logic gates that are part of a standard cell library . The available combinational gates are listed in the table below along with information about their timing, loading and size. You can access the library by starting your netlist with the following include statements: .include "/mit/6.004/jsim/nominal.jsim" .include "/mit/6.004/jsim/stdcell.jsim" Everyone should use the provided cells in creating their design. The timings have been taken from a 0.18 micron CMOS process measured at room temperature.
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6.004 Computation Structures - 2 - Lab #3 Netlist Function t CD (ns) t PD (ns) t R (ns/pf) t F (ns/pf) load (pf) size ( μ 2 ) Xid z constant0 0 = Z 0 Xid z constant1 1 = Z 0 Xid a z inverter .005 .02 2.3 1.2 .007 10 Xid a z inverter_2 .009 .02 1.1 .6 .013 13 Xid a z inverter_4 .009 .02 .56 .3 .027 20 Xid a z inverter_8 A Z = .02 .11 .28 .15 .009 56 Xid a z buffer .02 .08 2.2 1.2 .003 13 Xid a z buffer_2 .02 .07 1.1 .6 .005 17 Xid a z buffer_4 .02 .07 .56 .3 .01 30 Xid a z buffer-8 A Z = .02 .07 .28 .15 .02 43 Xid e a z tristate .03 .15 2.3 1.3 .004 23 Xid e a z tristate_2 .03 .13 1.1 .6 .006 30 Xid e a z tristate_4 .02 .12 .6 .3 .011 40 Xid e a z tristate_8 A Z = when e=1 else Z not driven .02 .11 .3 .17 .02 56 Xid a b z and2 B A Z = .03 .12 4.5 2.3 .002 13 Xid a b c z and3 C B A Z = .03 .15 4.5 2.6 .002 17 Xid a b c d z and4 D C B A Z = .03 .16 4.5 2.5 .002 20 Xid a b z nand2 B A Z = .01 .03 4.5 2.8 .004 10 Xid a b c z nand3 C B A Z = .01 .05 4.2 3.0 .005 13 Xid a b c d z nand4 D C B A Z = .01 .07 4.4 3.5 .005 17 Xid a b z or2 B A Z + = .03 .15 4.5 2.5 .002 13 Xid a b c z or3 C B A Z + + = .04 .21 4.5 2.5 .003 17 Xid a b c d z or4 D C B A Z + + + = .06 .29 4.5 2.6 .003 20 Xid a b z nor2 B A Z + = .01 .05 6.7 2.4 .004 10 Xid a b c z nor3 C B A Z + + = .02 .08 8.5 2.4 .005 13 Xid a b c d z nor4 D C B A Z + + + = .02 .12 9.5 2.4 .005 20 Xid a b z xor2 B A Z = .03 .14 4.5 2.5 .006 27 Xid a b z xnor2 B A Z = .03 .14 4.5 2.5 .006
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lab3 - MASSACHUSETTS INSTITUTE OF TECHNOLOGY DEPARTMENT OF...

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