lect.06.Compiler.4up

lect.06.Compiler.4up - Announcements TBD EE108B Lecture 6...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
EE108b Lecture 6 C. Kozyrakis 1 EE108B – Lecture 6 Performance and Compilers Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b EE108b Lecture 6 C. Kozyrakis 2 Announcements • TBD EE108b Lecture 6 C. Kozyrakis 3 CPU Execution Time • CPU Execution Time • To improve performance (i.e., reduce execution time) – Increase clock rate (decrease clock cycle time) OR – Decrease CPI OR – Reduce the number of instructions • Designers balance cycle time against the number of cycles required – Improving one factor may make the other one worse… Time Cycle Clock CPI ns Instructio Time Execution × × = Rate Clock CPI ns Instructio Time Execution × = EE108b Lecture 6 C. Kozyrakis 4 Clock Rate ≠ Performance • Mobile Intel Pentium 4 Vs Intel Pentium M – 2.4 GHz 1.6 GHz • Performance on Mobilemark with same memory and disk – Word, excel, photoshop, powerpoint, etc. – Mobile Pentium 4 is only 15% faster • What is the relative CPI? – ExecTime = IC • CPI/Clock rate – IC • CPI M /1.6 = 1.15 • IC • CPI 4 /2.4 – CPI 4 /CPI M = 2.4/(1.15•1.6) = 1.3
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EE108b Lecture 6 C. Kozyrakis 5 CPI Varies • Different instruction types require different numbers of cycles • CPI is often reported for types of instructions • where CPI i is the CPI for the type of instructions and IC i is the count of that type of instruction = × = n i i i IC CPI Cycles Clock 1 ) ( EE108b Lecture 6 C. Kozyrakis 6 Computing CPI • To compute the overall average CPI use = × = n i i i Count n Instructio Count n Instructio CPI CPI 1 EE108b Lecture 6 C. Kozyrakis 7 Computing CPI Example Given this machine, the CPI is the sum of CPI × Frequency Average CPI is 0.5 + 0.4 + 0.4 + 0.2 = 1.5 What fraction of the time for data transfer? Instruction Type CPI Frequency CPI * Frequency ALU 1 50% 0.5 Branch 2 20% 0.4 Load 2 20% 0.4 Store 2 10% 0.2 EE108b Lecture 6 C. Kozyrakis 8 What is the Impact of Displacement Based Memory Addressing Mode? Assume 50% of MIPS loads and stores have a zero displacement. Instruction Type CPI Frequency CPI * Frequency ALU 1 50% 0.5 Branch 2 20% 0.4 Load 2 20% 0.4 Store 2 10% 0.2
Background image of page 2
EE108b Lecture 6 C. Kozyrakis 9 • Two different compilers are being tested for a 1 GHz. machine with three different classes of instructions: Class A, Class B, and Class C, which require 1, 2, and 3 cycles (respectively). Both compilers are used to produce code for a large piece of software. The first compiler's code uses 5 million Class A instructions, 1 million Class B instructions, and 1 million Class C instructions. The second compiler's code uses 10 million Class A instructions, 1 million Class B instructions, and 1 million Class C instructions. • Which sequence will be faster according to MIPS?
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 11

lect.06.Compiler.4up - Announcements TBD EE108B Lecture 6...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online