lect.08.PipelinedProcessor.4up

lect.08.PipelinedProcessor.4up - EE108b Lecture 8 C....

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Unformatted text preview: EE108b Lecture 8 C. Kozyrakis 1 Lecture 8 Simple & Pipelined Processor Designs Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b EE108b Lecture 8 C. Kozyrakis 2 Announcements Upcoming deadlines HW2 due today PA1 due on Thursday 2/8 Quiz 1 review session on Friday Quiz 1 Tue 2/6, 7pm9pm, location TBD Local SCPD students must come to Stanford for the midterm Covers lectures 1-7 Closed book, 1 page of notes + green card, calculator EE108b Lecture 8 C. Kozyrakis 3 Review: How to Execute Instructions First we need to: Fetch the instruction Then we need to: Decode instruction / fetch register operands Then we need to: Do the operation Then we need to: Write the result into register-file Finally we need to: Calculate the next instruction address EE108b Lecture 8 C. Kozyrakis 4 Review: Datapath for Instruction Fetch Unit PC Instruction memory Read address Instruction [31 0] Add 4 EE108b Lecture 8 C. Kozyrakis 5 Review: Datapath for Arithmetic & Logical Instructions Instruction [31 0] Instruction [20 16] Instruction [25 21] ALUO p RegWrite RegDst ALUSrc 16 32 Instruction [15 0] M u x 1 Registers W rite register W rite data Read data 1 Read data 2 Read register 1 Read register 2 Zero extend M u x 1 ALU result Zero Instruction [15 11] ALU Sign or EE108b Lecture 8 C. Kozyrakis 6 Review: Load Datapath Extend datapath to support other immediate operations Extender handles either sign or zero extension MUX selects between ALU result and Memory output Instruction [31 0] Instruction [20 16] Instruction [25 21] MemtoReg ALUO p MemWrite RegWrite MemRead RegDst ALUSrc 16 32 Instruction [15 0] M u x 1 Registers W rite register W rite data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend M u x 1 ALU result Zero Data memory Write data Read data M u x 1 Instruction [15 11] ALU Address EE108b Lecture 8 C. Kozyrakis 7 Review: Store Datapath Read Register 2 is passed on to Memory Memory address calculated just as in lw case Instruction [31 0] Instruction [20 16] Instruction [25 21] MemtoReg ALUO p MemWrite RegWrite MemRead RegDst ALUSrc 16 32 Instruction [15 0] M u x 1 Registers W rite register W rite data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend M u x 1 ALU result Zero Data memory Write data Read data M u x 1 Instruction [15 11] ALU Address EE108b Lecture 8 C. Kozyrakis 8 Putting it All Together Instruction [31 0] Instruction [20 16] Instruction [25 21] MemtoReg ALUO p MemWrite RegWrite MemRead RegDst ALUSrc 16 32 Instruction [15 0] M u x 1 Registers W rite register W rite data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend M u x 1 ALU result Eq Data memory Write data Read data M u x 1 Instruction [15 11] ALU Address PC Instruction memory Read address Instruction [31 0] Add 4 Add ALU result M u x 1 Shift left 2 Jump Instruction [25 0...
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lect.08.PipelinedProcessor.4up - EE108b Lecture 8 C....

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