lect.09.PipelinedHazards.4up

lect.09.PipelinedHazards.4up - Announcements PA-1 is due...

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EE 108b Lecture 9 C. Kozyrakis 1 Lecture 9 Pipeline Hazards Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b EE 108b Lecture 9 C. Kozyrakis 2 Announcements • PA-1 is due today – Electronic submission • Lab2 is due on Tuesday 2/13 th • Quiz1 grades will be available next week – Solutions will be posted on line tomorrow • Tuesday 2/13 th lecture will be a video playback – Can come to lecture hall or watch from home or offline EE 108b Lecture 9 C. Kozyrakis 3 Review: Single-cycle Datapath (load instruction) IF: Instruction Fetch – Fetch the instruction from memory – Increment the PC by 4 RF/ID: Register Fetch and Instruction Decode – Fetch base register EX: Execute – Calculate base + sign-extended immediate MEM: Memory – Read the data from the data memory WB: Write back – Write the results back to the register file IF RF/ID EX MEM WB Load Clk EE 108b Lecture 9 C. Kozyrakis 4 Review: Multi-cycle Datapath • Divide datapath into steps – Each step is one clock cycle – Note RF is a short cycle, but waits for clock R e g s Data Memory IF Instruction Fetch RF Register Fetch EX Execution MEM. Memory WB Write back ALU Instr. Memory P C R e g s
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EE 108b Lecture 9 C. Kozyrakis 5 Review: Full Pipeline • Fetch a new instruction each cycle – Each stage of the pipeline is working on a different instruction R e g s Data Memory IF Instruction Fetch RF Register Fetch EX Execution MEM. Memory WB Write back ALU Instr. Memory R e g s EE 108b Lecture 9 C. Kozyrakis 6 Review: Pipelining Load • Load instruction takes 5 stages – Five independent functional units work on each stage • Each functional unit used only once – Another load can start as soon as 1 st finishes IF stage – Each load still takes 5 cycles to complete – The throughput , however, is much higher Clock Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 IF RF/ID EX MEM WB 1st lw IF RF/ID EX MEM WB 2nd lw IF RF/ID EX MEM WB 3rd lw EE 108b Lecture 9 C. Kozyrakis 7 Pipeline Datapath tion ory 4 32 0 Add Add result Shift left 2 In struct ion IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Address Data memory Instruc mem Address IF ID EX MEM WB EE 108b Lecture 9 C. Kozyrakis 8 Important ISA Issues • Instruction length – Fixed MIPS instruction length allows easy pipeline even though decode does not happen until the second stage – Intel 80x86 has a much more challenging problem where instructions vary from 1-17 bytes • Instruction formats – Register access possible even though decode does not happen until second stage due to regularity of formats • Limited memory access – Since only loads and stores access memory, other instructions do not need to use the ALU to calculate the memory address before the actual computation
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EE 108b Lecture 9 C. Kozyrakis 9 Review: Control Signals add sub ori lw sw beq jump RegDst
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lect.09.PipelinedHazards.4up - Announcements PA-1 is due...

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