lect.10.PipelineHazards2.4up

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EE 108b Lecture 10 C. Kozyrakis 1 Lecture 10 Control Hazards and Advanced Pipelinning Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b EE 108b Lecture 10 C. Kozyrakis 2 Announcements Announcements will be made through email EE 108b Lecture 10 C. Kozyrakis 3 Review: Pipeline Hazards These are dependencies between instructions that are exposed by pipelining Causes pipeline to loose efficiency (pipeline stalls, wasted cycles) If all instructions are dependent No advantage of a pipelining (since all must wait) These limits to pipelining are known as hazards Structural Hazard (Resource Conflict) Two instructions need to use the same piece of hardware Data Hazard Instruction depends on result of instruction still in the pipeline Control Hazard Instruction fetch depends on the result of instruction in pipeline EE 108b Lecture 10 C. Kozyrakis 4 Reg Review: Data Hazard Example Dependencies forwards in time are hazard I n s t r. O r d e r Time (clock cycles) add r1 ,r2,r3 sub r4, r1 , r3 and r6, r1 , r7 or r8, r1 , r9 xor r10, r1 , r11 IF ID/RF EX MEM WB ALU Im Reg Dm ALU Im Reg Dm Reg ALU Im Reg Dm Reg Im ALU Reg Dm Reg ALU Im Reg Dm Reg
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EE 108b Lecture 10 C. Kozyrakis 5 Forwarding Hardware What does forwarding cost? Need to add stuff to datapath and stuff to control Datapath Need to add multiplexers to functional units Source to function unit could come from Register file • Memory ALU of last cycle ALU from two cycles ago Adding this mux increases the critical path of design Needs to be designed carefully EE 108b Lecture 10 C. Kozyrakis 6 Discovering Forwarding Paths in Pipelines Can get out of hand if not carefull Simple procedure Identify all pipeline stages that produce new values In our case, EX and MEM All pipeline stages after the earliest producer can be the source of a forwarded operand In our case, MEM Identify all pipeline stages that really consume values In our case, EX and MEM These stages are the destinations of a forwarded operand Add multiplexor for each pair of source/destination stages EE 108b Lecture 10 C. Kozyrakis 7 Forward Hardware - Datapath ID/EX EX/MEM MEM/WB Data Memory ALU MuxB MuxA EE 108b Lecture 10 C. Kozyrakis 8 Forward Hardware - Control Need to decide which multiplexer input to enable Doesn’t seem that hard but it can get troublesome Especially with machines that issue multiple instructions/cycle Which is the correct result Need to tag ALU, MEM results with registerID Need to compare register fetch with tags All this takes hardware, but can be done in parallel Need to find youngest version of the register Multiple tags can match Need to find freshest version of the data
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EE 108b Lecture 10 C. Kozyrakis 9 Forward Hardware - Datapath & Control 1 add r1, r2, r3 sub r4, r1, r3 EE 108b Lecture 10 C. Kozyrakis 10 Forward Hardware - Datapath & Control 2 add r1, r2, r3 sub r4, r1, r3 or r6, r1, r7 EE 108b Lecture 10 C. Kozyrakis 11
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