lect.12.Memory.4up

lect.12.Memory.4up - Announcements Lecture 12 Memory Design...

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EE 108b Lecture 12 C. Kozyrakis 1 Lecture 12 Memory Design & Caches, part 2 Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b EE 108b Lecture 12 C. Kozyrakis 2 Announcements • HW3 is due today • PA2 is available on-line today – Part 1 is due on 2/27 – Part 2 is due on 3/6 • HW4 available on-line today – Merged with HW5 – Due on 3/13 EE 108b Lecture 12 C. Kozyrakis 3 Review: Memory Technologies • The cheaper the memory, – The slower the access times $0.5-$2 5-10 ms Disk $100-$200 50-120 ns DRAM $4000–$10000 0.5-25 ns SRAM $/GB in 2004 Access Time Technology EE 108b Lecture 12 C. Kozyrakis 4 Review: The Processor-Memory Performance Gap • A 1-cycle access to DRAM memory in 1980 takes 100s of cycles now We can’t afford to stall the pipeline for that long! µProc 55%/yr. DRAM 7%/yr. 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 48% / year) Performance “Moore’s Law”
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EE 108b Lecture 12 C. Kozyrakis 5 Review: Memory Hierarchy Tradeoff cost-speed and size-speed using a hierarchy of memories: – small, fast, expensive caches at the top – large, slow, and cheap memory at the bottom M C Small Fast Expensive M M Big, Slow, Cheap Big Fast Cheap •We can’t use large amounts of fast memory –expensive in dollars, watts, and space •Ideal: the memory hierarchy should be almost as fast as the top level, and almost as big and cheap as the bottom level •Program locality makes this possible EE 108b Lecture 12 C. Kozyrakis 6 Review: Typical Memory Hierarchy: Everything is a Cache for Something Else Access time Capacity Managed by 1cycle ~500B software/compiler 1-3cycles ~64KB hardware 5-10cycles 1MB hardware ~100cycles ~2GB Software/OS 10 6 -10 7 cycles ~100GB software/OS Registers Level 1 Cache Level 2 Cache CPU Chip DRAM Chips Mechanical Devices Disk Tape EE 108b Lecture 12 C. Kozyrakis 7 How To Build A Cache? • Big question – I need to map a large address space into a small memory • Want associative lookup • How do I do that? – Can build full associative lookup in hardware, but complex – Need to find a simple but effective solution – Two common techniques: • Direct Mapped • Set Associative • Details – Block size – Write policy – Replacement policy EE 108b Lecture 12 C. Kozyrakis 8 Direct Mapped Caches • Access with these is a straightforward process: – Index into the cache with block number modulo cache size – Read out both data and “tag” (stored upper address bits) – Compare Tag with address you want to determine hit/miss – Need valid bit for empty cache lines Cache Index 0 1 2 3 2 - 1 n : 2 n Bytes Data Byte 0 Byte 1 Byte 2 Byte 3 Byte 2 n -1 0 n 31 : Cache Tag: 0x50 : 0x03 0x50 Valid Bit : Tag
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EE 108b Lecture 12 C. Kozyrakis 9 Cache Blocks • Previous example had only 1 byte blocks – Strategy took advantage of temporal locality since if a byte is referenced, it will tend to be referenced soon – Did not take advantage of spatial locality • To take advantage of spatial locality, increase block size – Another advantage: Reduces size of tag memory, too!
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This note was uploaded on 03/08/2011 for the course EE 108B at Stanford.

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lect.12.Memory.4up - Announcements Lecture 12 Memory Design...

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