lect.15.OS3.4up

lect.15.OS3.4up - Announcements PA2.2 due on 3/6 EE108B...

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EE108b Lecture 15 C. Kozyrakis 1 EE108B Lecture 15 Virtual Memory II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b EE108b Lecture 15 C. Kozyrakis 2 Announcements • PA2.2 due on 3/6 EE108b Lecture 15 C. Kozyrakis 3 Review: Levels in Memory Hierarchy CPU CPU regs regs C a c h e Memory Memory disk disk size: Speed(cycles): $/Mbyte: block size: 128 B 0.5-1 8 B Register Cache Memory Disk Memory <4MB 1-20 $30/MB 32 B < 16 GB 80-100 $0.128/MB 8 KB > 100 GB 5-10 M $0.001/MB larger, slower, cheaper 8 B 32 B 8 KB cache virtual memory EE108b Lecture 15 C. Kozyrakis 4 Review: Page Faults (Similar to “Cache Misses”) • What if an object is on disk rather than in memory? – Page table entry indicates virtual address not in memory – OS exception handler invoked to move data from disk into memory • current process suspends, others can resume • OS has full control over placement, etc. CPU Memory Page Table Disk Virtual Addresses Physical Addresses CPU Memory Page Table Disk Virtual Addresses Physical Addresses Before fault After fault
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EE108b Lecture 15 C. Kozyrakis 5 Review: Page Tables Page table entry contains access rights information – hardware enforces this protection (trap into OS if violation occurs) Page Tables Process i: Physical Addr Read? Write? PP 9 Yes No PP 4 Yes Yes XXXXXXX No No VP 0: VP 1: VP 2: Process j: 0: 1: N-1: Memory Physical Addr Read? Write? PP 6 Yes Yes PP 9 Yes No XXXXXXX No No VP 0: VP 1: VP 2: EE108b Lecture 15 C. Kozyrakis 6 Review: Page Table Problems • “Internal” Fragmentation resulting from fixed size pages since not all of page will be filled with data – Problem gets worse as page size is increased • Each data access now takes two memory accesses – First memory reference uses the page table base register to lookup the frame – Second memory access to actually fetch the value • Page tables are large – Consider the case where the machine offers a 32 bit address space and uses 4 KB pages • Page table contains 2 32 / 2 10 = 2 22 entries • Assume each entry contains ~32 bits • Page table requires 4 MB of RAM per process! EE108b Lecture 15 C. Kozyrakis 7 Review:TLB Entries • Just holds a cached Page Table Entry (PTE) • Additional bits for LRU, etc. may be added • Optimization is to access TLB and cache in parallel Virtual Page Physical Frame Dirty LRU Valid Access Rights TLB Lookup Cache Main Memory Virtual Addr Phy Addr miss hit data hit miss CPU map entry data Access page tables for translation (from memory!) EE108b Lecture 15 C. Kozyrakis 8 Review: TLB Miss Handler • A TLB miss can be handled by software or hardware – Miss rate : 0.01% – 1% – Page tables are stored in regular physical memory – It is therefore likely that the data is in the L2 cache • In software, a special OS handler looks up the value in the page table – Seven to ten instructions on R3000/R4000 • In hardware, microcode or a dedicated finite state machine (FSM)
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This note was uploaded on 03/08/2011 for the course EE 108B at Stanford.

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lect.15.OS3.4up - Announcements PA2.2 due on 3/6 EE108B...

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