lect.17.IO-buses.4up - Announcements Remaining deliverables...

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EE108b Lecture 17 C. Kozyrakis 1 EE108B Lecture 17 I/O Buses and Interfacing to CPU Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b EE108b Lecture 17 C. Kozyrakis 2 Announcements Remaining deliverables – PA2.2. today – HW4 on 3/13 – Lab4 on 3/19 In class Quiz 2 on Thu 2/15 (11am – 12.30pm) – Closed-books, 1 page of notes, green page, calculator – All lectures included – SCPD students come to class for exam Advice – Catch up with lectures and textbook – Take advantage of office hours and discussion sessions Last review session on Friday EE108b Lecture 17 C. Kozyrakis 3 I/O Review I/O Performance is dependent upon many factors – Device performance, which is usually technology driven – CPU and memory system performance – Software efficiency (OS) – Workload being measured Consider the example of disk performance – Three major types of mechanical delays • Seek time – Time to move head over correct track • Rotational delay – Time for sector to rotate under head • Transfer time – Time to read data from disk – Transaction processing • Lots of concurrent requests • Instruction behavior – deep pipelines don’t work well • Memory access – random access to large data • Disk access – small files without locality EE108b Lecture 17 C. Kozyrakis 4 Today’s Lecture • Buses • Interfacing I/O with processor and memory • Read Sections 8.4–8.9
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EE108b Lecture 17 C. Kozyrakis 5 Buses • A bus is a shared communication link that connects multiple devices • Single set of wires connects multiple “subsystems” as opposed to a point to point link which only connects two components together • Wires connect in parallel, so 32 bit bus has 32 wires of data Memory Processor I/O Device I/O Device I/O Device EE108b Lecture 17 C. Kozyrakis 6 Advantages/Disadvantages Advantages – Broadcast capability of shared communication link – Versatility • New device can be added easily • Peripherals can be moved between computer systems that use the same bus standard – Low Cost • A single set of wires is shared multiple ways Disadvantages – Communication bottleneck • Bandwidth of bus can limit the maximum I/O throughput – Limited maximum bus speed • Length of the bus • Number of devices on the bus • Need to support a range of devices with varying latencies and transfer rates EE108b Lecture 17 C. Kozyrakis 7 Bus Organization • Bus Components – Control Lines • Signal begin and end of transactions • Indicate the type of information on the data line – Data Lines • Carry information between source and destination • Can include data, addresses, or complex commands Data Lines Control Lines EE108b Lecture 17 C. Kozyrakis 8 Types of Buses Processor-Memory Bus (or front-side bus or system bus) – Short, high-speed bus – Connects memory and processor directly – Designed to match the memory system and achieve the maximum memory-to-processor bandwidth (cache transfers)
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lect.17.IO-buses.4up - Announcements Remaining deliverables...

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