Rs04 - 1 EE 108B Review Session#4 Daxia Ge Friday February 9 th 2007 2 Admin • Quiz#1 feedback • PA1 – already due Nothing until next week

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Unformatted text preview: 1 EE 108B Review Session #4 Daxia Ge Friday February 9 th , 2007 2 Admin • Quiz #1 - feedback • PA1 – already due. Nothing until next week. • Lab2 – due Tuesday • HW3 – out next week • Tape-ahead lecture Tuesday 3 Quiz #1 4 Pipeline: motivation 5 6 Pipelining • Terms: – Latency vs. Throughput – Dependencies vs. Hazards – Forwarding vs. Bypassing – Interlocking – MIPS vs. MIPS 7 Test your understanding 1. Short Questions a. To increase throughput, the Intel Pentium 4 has a 20 stage pipeline while the AMD Athlon XP has only 9 stages. The Intel processor is therefore able to achieve a much higher throughput. In practice however, this is not necessarily the case. Give the most significant reason why the Intel Pentium 4 does not complete operations at twice the rate of the Athlon. 8 Test your understanding (cont’) b. You need to make a choice between a pipelined MIPS implementation without any bypassing or interlocking and one with bypassing and interlocking. You know exactly which programs you are going to execute. Why might you get better performance from the implementation without any bypassing or interlocking? 9 MIPS: Pipelined • MIPS was designed with pipelining in mind: – Split I & D memory – Fixed length instructions – Limited/fixed instruction formats – Memory accesses limited to load/stores – Memory access are aligned – Write before Read* 10...
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This note was uploaded on 03/08/2011 for the course EE 108B at Stanford.

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Rs04 - 1 EE 108B Review Session#4 Daxia Ge Friday February 9 th 2007 2 Admin • Quiz#1 feedback • PA1 – already due Nothing until next week

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