Lab 3 Register Design

Lab 3 Register Design - Lab 3: Register (Flip-flop) Design...

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Lab 3: Register (Flip-flop) Design and Characterization Objectives 1) Design a CMOS D-Latch. 2) Understand the operation of a bistable circuit. 3) Design an edge-triggered CMOS master-slave flip-flop. 4) Verify the operation by configuring the register as a divide-by-two circuit Background Master-slave type registers are commonly used in almost any synchronous (involving a global clock signal) digital system. As shown below, in a typical synchronous digital system, a combinational data path exists between the two flip-flops. The flip-flops are used to coordinate the data flow and therefore the overall timing characteristics of the system. The first flip-flop is referred to as the launching register since the data flow starts when the active edge of the clock signal arrives to this register. In the next active edge of the clock signal, the result of computation is latched into the second register. The second register is therefore referred to as the capturing register. Two inequalities need to be satisfied for this synchronous circuit to work properly: The first inequality states that the clock period has to be greater than the summation of the data path delay (shown in the figure) and setup time of the second register. If this condition is not satisfied, the circuit should be slowed down by decreasing the frequency. Another solution is to insert an additional register to divide the combinational circuit into two smaller sections with less delay. The second inequality states that the data path delay should be greater than the hold time
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of the second register. If this condition is not satisfied, the circuit may fail since the valid data
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This note was uploaded on 03/16/2011 for the course ESE 324 taught by Professor Sussman-fort,s during the Spring '08 term at SUNY Stony Brook.

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Lab 3 Register Design - Lab 3: Register (Flip-flop) Design...

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