Lab 2 Phase detector

# Lab 2 Phase detector - Lab 2 XOR Based Phase Detector...

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Unformatted text preview: Lab 2: XOR Based Phase Detector Design Objectives 1) Design a simple XOR based phase detector. 2) Understand the fundamental design constraints of a phase detector such as maximum operating speed, and dead zone. 3) Design two different implementations of a phase detector. 4) Understand the differences between a transmission gate based phase detector and static CMOS based phase detector. Background Phase detector is a circuit that produces an output signal whose average value is linearly proportional to the phase difference between the two inputs. Referring to the following figure, the slope of the line is referred to as the gain of the phase detector. The output is voltage and input is a phase difference so the gain is measured in V/rad. A phase detector is a highly important circuit block for a variety of applications including motor control and telecommunication systems. A simple phase detector can be implemented as an XOR gate. As shown in the figure below, the width of the output pulse varies as the phase difference between the inputs varies. The average DC value of the output signal is proportional to the phase difference of the input signals. Two important design specifications of a phase detector are maximum operating frequency and dead zone. The first one refers to the highest frequency of the input signals for which the phase detector can reliably produce the output. The second specification refers to the minimum phase difference that the phase detector can reliably detect. The condition to determine the maximum operating frequency may vary based on the application. In this experiment, we will assume the following condition: Condition to determine the maximum operating frequency: Phase detector is considered to reliably detect the phase if the output reaches to at least 70% of the Vdd (in our case this is equal to 3.5 volts) when the input signal is at half the bit period. This condition is described in the figure below. Assume the other input is connected to Vdd, so phase detector functions as an inverter....
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## This note was uploaded on 03/16/2011 for the course ESE 324 taught by Professor Sussman-fort,s during the Spring '08 term at SUNY Stony Brook.

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Lab 2 Phase detector - Lab 2 XOR Based Phase Detector...

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