cosc3330-hw2-q4-extra - (for only those used based on the...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Execution/Address Calculation stage control lines Memory access stage control lines Write-back stage control lines Instruction Reg Dst ALU Op1 ALU Op0 ALU Src Branch Mem Read Mem Write Reg write Mem to Reg R-format 1 1 0 0 0 0 0 1 0 lw 0 0 0 1 0 1 0 1 1 sw X 0 0 1 0 0 1 0 X beq X 0 1 0 1 0 0 0 X 4. Extra Credit (30 points, equivalent to 3 points in final grade). Due to data hazards, the processor requires a forwarding logic unit to handle true dependency in the following code to get rid of pipeline bubbles. The pipeline shown below is simplified to the relevant part for forwarding. Please fill in the blanks of Table 2 . There are five input signals going into the forwarding unit and two output signals generated by the forwarding unit. Also fill in the data signals that go into the ALU. Please use the correct data values
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: (for only those used) based on the given code. Assume each data memory byte is loaded with the least significant byte of its own address. For example, 0x00000001 contains 0x01, 0x00000002 contains 0x02, 0x0000003F contains 0x3F, etc. Thus, if you load word (lw) from 0x00000000, you will get 0x03020100; lw from 0x00000008 will get 0x0B0A0908. Also assume that each register contains a value equal to the register number prior to execution of the first instruction. This means $12 contains value 12. Figure 5. Forwarding Table 2: Signals A B C D E F X Y O P Q W V M 0x10020000: lw $15, 8($12) addi $9, $7, -4 sub $13, $15, $9 sw $13, 12($9) add $16, $9, $11...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online