CompArch-Lec09-Pipelining-2

CompArch-Lec09-Pipelining-2 - Lecture 9 Pipelining –...

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Unformatted text preview: Lecture 9. Pipelining – Cont’d COSC3330 Computer Architecture Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston Topic • Pipelining (cont’d) MIPS Encoding: I-Type 31 opcode rs rt Immediate Value 26 25 21 20 16 15 lw $5, 3000($2) Immediate rs rt sw $5, 3000($2) Immediate rs rt Datapath Control Signals 32 32 Xra Yra Zwa Ydo Xdo Zdi 5 5 5 32 RegFile RegFile Clock we 32 32 32 A B ALU ALU ā /s LF ST SD 4 2 ALS 2 Sign-extended immediate 32 1 Memory Memory Memory Memory Address Data msel r/w ld enable st enable imm enable 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag 0001: AND 0011: A 0101: B 0110: XOR 0111: OR sw $5, 8($2) Modified Datapath for I-Type 32 32 Xra Yra Zwa Ydo Xdo Zdi 5 5 5 32 RegFile RegFile Clock we 32 32 32 A B ALU ALU ā /s LF ST SD 4 2 ALS 2 Sign-extended immediate 32 1 Memory Memory Memory Memory Address Data msel r/w ld enable st enable imm enable 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag 0001: AND 0011: A 0101: B 0110: XOR 0111: OR offset Modified Datapath for I-Type 32 32 Xra Yra Zwa Ydo Xdo Zdi 5 5 5 32 RegFile RegFile Clock we 32 32 32 A B ALU ALU ā /s LF ST SD 4 2 ALS 2 Sign-extended immediate 32 1 Memory Memory Memory Memory Address Data msel r/w ld enable st enable imm enable 00: AU 01: LU 10: SU 11: Disable ALU Shift Type (ST) 00: No Shift 01: Logical 10: Arithmetic 11: Rotate Shift Direction (SD) 0: Left 1: Right Logical Flag 0001: AND 0011: A 0101: B 0110: XOR 0111: OR offset Pipelining 7 Instruction Fetch Register File Access (Read) ALU Operation Data Access Register Access (Write) 2ns 1ns 2ns 2ns 1ns 2 4 6 8 10 12 14 16 18 T im e lw $ 1 , 1 0 0 ($ 0 ) lw $ 2 , 2 0 0 ($ 0 ) lw $ 3 , 3 0 0 ($ 0 ) P ro g ra m e x e c u tio n o rd e r (in in s tr u c tio n s ) 2 4 6 8 10 12 14 T im e lw $ 1 , 1 0 0 ($ 0 ) lw $ 2 , 2 0 0 ($ 0 ) lw $ 3 , 3 0 0 ($ 0 ) P ro g ra m e x e c u tio n o rd e r (in in s tru c tio n s ) Pipelined Execution Sequential Execution Multi-cycle Datapath vs. Pipelining • Break up the instructions into steps • Each step takes a cycle • Instructions may take different number of cycles to finish • Fetch next instruction only after the previous one completes all steps • Try to fetch a new instruction in each cycle • Multiple instructions are being executed simultaneously • May stall due to hazards s Structure hazards s Data hazard s Control hazard • Reduce pipeline stalls s Forwarding s Multiported memory s Branch delay slot/branch prediction Multi-cycle Datapath (No Pipelining) Pipelining • Unclocked vs. Clocked • Clocks used in synchronous logic s when should an element that contains state be updated?...
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This note was uploaded on 03/18/2011 for the course COSC 3330 taught by Professor Notknown during the Spring '11 term at University of Houston.

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CompArch-Lec09-Pipelining-2 - Lecture 9 Pipelining –...

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