CompArch-Lec08-Pipelining - COSC3330 Computer Architecture...

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Lecture 8. Pipelining COSC3330 Computer Architecture Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston
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Next Pipelining Hazard
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Instruction Execution Instruction Memory μ ROM ROM 32 32 Ydo Xdo Zdi 32 RegFile we 32 32 32 A B ALU ALU 4 2 2 Sign-extended immediate 32 1 0 Memory Address Data msel r/w Program Counter 32 + 4 beq bne (if true) ext Offset Offset mux ext Target Target addr addr jr j jr/j Instruction Register 32 + addr data I-Fetch Decode Execute Memory Write Result
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Instruction Execution 5 basic steps square4 fetch instruction (F) square4 decode instruction/read registers (R) square4 execute (X) square4 access memory (M) square4 store result (W)
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Execution Datapath 32 32 Xra Yra Zwa Ydo Xdo Zdi 5 5 5 32 RegFile Clock we 32 32 32 A B ALU ALU ā /s LF ST SD 4 2 ALS 2 Sign-extended immediate 32 1 0 Memory Address Data msel r/w ld enable st enable imm enable
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Address 0 u 1 Instruction Memory Address Instruction Data Memory Address Read data Write data Xdo RegFile Ydo Xra Yra Zra Zdi 1 0 1 0 x 1 0 Sign Ext Shift Left 2 + + PC 4 Execution Datapath
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Control Flow Support Microcode ROM Instruction Memory addr data Program Counter 32 + 4 beq bne (if true) ext Offset (from Offset (from μ ROM) 0 1 mux mux 0 1 mux ext Target Target addr addr (from μ ROM) ROM) jr j jr/j Instruction Register 32 rs + 0 1 mux Datapath 32x32 RegFile
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Address 0 u 1 Instruction Memory Address Instruction Data Memory Address Read data Write data Xdo RegFile Ydo Xra Yra Zra Zdi 1 0 1 0 x 1 0 Sign Ext Shift Left 2 + + PC 4 Control Flow Support
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Datapath Timing 9 Instruction execution time = ? Clock frequency = ? 0 u 1 Instruction Memory Address Instruction Data Memory Address Read data Write data Xdo RegFile Ydo Xra Yra Zra Zdi 1 0 1 0 x 1 0 Sign Ext Shift Left 2 + + PC 4 2ns 1ns 2ns 2ns 1ns Clock rate = 10 9 / 8 = 125MHz Instruction Fetch Instruction Decode/ RegFile Read Execute/Addr Cal Mem Access Write Back
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Processor Performance Performance of single-cycle processor is limited by the long critical path delay square4 The critical path limits the operating clock frequency Can we do better? square4 New semiconductor technology will reduce the critical path delay by manufacturing small-sized transistors Core 2 Duo is manufactured with 65nm technology Core i7 is manufactured with 45nm technology square4 Can we increase the processor performance with a different microarchitecture? Yes! Pipelining 10
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Revisiting Performance 11 Laundry Example square4 Ann, Brian, Cathy, Dave each has one load of clothes to wash, dry, and fold square4 Washer takes 30 minutes square4 Dryer takes 40 minutes square4 Folder takes 20 minutes A B C D
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Sequential Laundry 12 Response time: Throughput: A B C D 30 40 20 30 40 20 30 40 20 30 40 20 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time 90 mins 0.67 tasks / hr (= 90mins/task, 6 hours for 4 loads)
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Pipelined Laundry 13 A B C D 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time 30 40 40 40 40 20 90 mins 1.14 tasks / hr (= 52.5 mins/task, 3.5 hours for 4 loads) Response time: Throughput: Pipelining doesn’t help latency (response time) of a single task
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