Unformatted text preview: 2. Suppose that if the dimensions of this process are shrunk by a factor of S , R eq scales as 1/S 2 , C scales as 1/S , and t buf scales as 1/S 2 . What is the expression for optimal number of buffers as a function of S ? What is the number if S=2 . Problem 4. For a simple level restorer shown in Fig 640 (p. 275) implemented in 1.2um technology, let capacitance at point X to ground C X =50fF , M r has effective W/L =1.8/1.5, M n has effective W/L =1.8/0.9. Assume the output inverter doesn’t switch, until its input equals V DD /2 . a. How long it takes M n to pull down node X from 5V to 2.5V if A =0V and B =5V ( hint: at Vx =5V, M n is saturated and M r is off. at Vx =2.5V, both M n and M r are in linear region). b. How long it takes M n to pull up node X from 0V to 2.5V when A=B =5V. c. What is the value of V B necessary to pull down Vx to 2.5V when A =0V? F= ABC+ACD Vout 7.2/1.2 Vdd A B...
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 Spring '09
 Mohammadi
 Integrated Circuit, Transistor, Logic gate, pmos transistor

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