HW50[1] - 2. Suppose that if the dimensions of this process...

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Homework 5 ECE456 Due: March 10 Problem 1: Implement the function below (both the function and its complement) in DCVSL (see page 267 of your textbook). Assume A, B, C, D and their complements are available as inputs. Make sure to use the minimum number of transistors. Problem 2: The following network is a pass transistor logic gate implemented in 1.2μm CMOS technology (see file spice_1.2um_CMOS.doc on Vista). 1. Determine the truth table for the circuit. What logic function does it implement? 2. Assuming 0 and 5V inputs, size the PMOS transistor to achieve a V OL =0.3V (hint for this case assume NMOS in linear regime and PMOS in Saturation). 3. If the PMOS were removed, would the circuit still function correctly? Does the PMOS transistor serve any useful purpose? Problem 3. Effects of scaling on pass-gate logic. 1. If a process has a t buf of 0.4nsec, R eq of 8Kohm, and C of 12fF, what is the optimal number of stages between buffers in a pass-gate chain?
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Unformatted text preview: 2. Suppose that if the dimensions of this process are shrunk by a factor of S , R eq scales as 1/S 2 , C scales as 1/S , and t buf scales as 1/S 2 . What is the expression for optimal number of buffers as a function of S ? What is the number if S=2 . Problem 4. For a simple level restorer shown in Fig 6-40 (p. 275) implemented in 1.2um technology, let capacitance at point X to ground C X =50fF , M r has effective W/L =1.8/1.5, M n has effective W/L =1.8/0.9. Assume the output inverter doesnt switch, until its input equals V DD /2 . a. How long it takes M n to pull down node X from 5V to 2.5V if A =0V and B =5V ( hint: at Vx =5V, M n is saturated and M r is off. at Vx =2.5V, both M n and M r are in linear region). b. How long it takes M n to pull up node X from 0V to 2.5V when A=B =5V. c. What is the value of V B necessary to pull down Vx to 2.5V when A =0V? F= ABC+ACD Vout 7.2/1.2 Vdd A B...
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