ch3_3 - distinguishing synchronous & asynchronous...

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1 9/2/2002 1 distinguishing synchronous & asynchronous transmission • asynchronous has ‘start bit’ & ‘stop bit ’ • asynchronous: clock runs unsynchronized with incoming signal • synchronous: clock runs synchronized with incoming signal 3.3.1 Bit Synchronization: - each frame transmitted as contiguous bit stream - receiver obtains & maintains bit synchronization in 1 of 2 ways 1. Clock Encoding : clock timing i nformation embedded in transmitted signal extracted by receiver 2. DPLL (digital phase locked loop): uses bit transitions in signal - receiver has local clock that is synchronized to signal by DPLL 3.3 Synchronous Transmission 2 general types of synchronous transmission: character oriented & bit oriented - both use same bit synchronization 9/2/2002 2 – 3 methods (i) Bipolar Encoding : uses RZ (return to zero)signal - signal: 3 signal levels: +,0,- - ‘1’ encoded by ‘+’ signal - ‘0’ encoded by ‘-‘ signal - return to 0 after each bit +V 0 -V 1 1 0 1 1 1 0 1 data tx clock RZ
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2 9/2/2002 3 (ii) Manchester or phase encoding: uses NRZ (Non Return Zero) signal - binary ‘1’ lo-hi transition - binary ‘0’ hi-lo transition always a transition at center of bit cell - used by clock extraction ckt - produce clock pulse in center of 2nd half of bit cell received encoded signal is either high (1) or low (0) signal shifted into SIPO how terminating wires are connected 1 1 0 1 1 1 0 1 data tx clock NRZ (1) detect edge (2) sample 9/2/2002 4 (iii) Differential Manchester Encoding • always a signal transition at center of each bit cell • transition at the start of a cell only if next bit = ‘0’ • encoded output takes on 1 of 2 forms, depending on assumed start level - either is just inverted form of the other - clock generated at end of each bit cell - transition determines if bit cell is ‘0’ or ‘1’ useful for TP links using differential drivers & receivers - doesn’t matter how terminating wires are connected 1 1 0 1 data tx clock NRZ,D (1) detect center transition for bit synch (2) edge transition indicates bit value
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3 9/2/2002 5 Manchester Schemes are balanced codes - no mean DC value - 000… or 111… will always have transitions (not constant DC signal) - important for AC coupling to receiver using transformer - receive electronics power supply isolated from transmission signal 2. DPLL (digital phase locked loop) alternative to clock encoding for bit synchronization • requires a sufficient transitions in bit stream resynchronize receiver’s clock • estimates bit timing in between edge transitions • scramble data or NRZI (i) pass data through scrambler before transmission • randomize bit stream
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ch3_3 - distinguishing synchronous & asynchronous...

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