slide9 - CPSC 321 Computer Architecture Designing a Single...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
CPSC 321 Computer Architecture Designing a Single Cycle Datapath Adapted from the lecture notes of John Kubiatowicz(UCB) and Praveen
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
The Big Picture: Where are We Now? ° The Five Classic Components of a Computer ° Today’s Topic: Design a Single Cycle Processor Control Datapath Memory Processor Input Output
Background image of page 2
The Big Picture: The Performance Perspective ° Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction ° Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction ° Today: Single cycle processor: - Advantage: One clock cycle per instruction - Disadvantage: long cycle time CPI Inst. Count Cycle Time
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
How to Design a Processor: step-by- step ° 1. Analyze instruction set => datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers - possibly more datapath must support each register transfer ° 2. Select set of datapath components and establish clocking methodology ° 3. Assemble datapath meeting the requirements ° 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. ° 5. Assemble the control logic
Background image of page 4
The MIPS Instruction Formats ° All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type ° The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction op target address 0 26 31 6 bits 26 bits op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Step 1a: The MIPS-lite Subset for today ° ADD and SUB addu rd, rs, rt subu rd, rs, rt ° OR Immediate: ori rt, rs, imm16 ° LOAD and STORE Word lw rt, rs, imm16 sw rt, rs, imm16 ° BRANCH: beq rs, rt, imm16 op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits
Background image of page 6
Logical Register Transfers ° RTL gives the meaning of the instructions ° All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORi R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt];PC <– PC + 4 BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 + sign_ext(Imm16)] || 00 else PC <– PC + 4
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Step 1: Requirements of the Instruction Set ° Memory instruction & data ° Registers (32 x 32) read RS read RT Write RT or RD ° PC ° Extender ° Add and Sub register or extended immediate ° Add 4 or extended immediate to PC
Background image of page 8
Step 2: Components of the Datapath ° Combinational Elements ° Storage Elements Clocking methodology
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 62

slide9 - CPSC 321 Computer Architecture Designing a Single...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online