slide10 - CPSC 321 Computer Architecture and Engineering...

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Unformatted text preview: CPSC 321 Computer Architecture and Engineering Lecture 7 Designing a Multi-cycle Processor Adapted from the lecture notes of John Kubiatowicz (UCB) Recap: A Single Cycle Datapath 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Equal Instruction<31:0> 1 1 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rt Rs nPC_sel Recap: The “Truth Table” for the Main Control R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) 1 1 x “R-type” 1 1 Or 1 1 1 1 Add x 1 x 1 1 Add x x 1 x Subtract x x x 1 x xxx op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 ALUop <2> 1 x ALUop <1> 1 x ALUop <0> 1 x Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3 RegDst ALUSrc : The Big Picture: Where are We Now? ° The Five Classic Components of a Computer ° Today’s Topic: Designing the Datapath for the Multiple Clock Cycle Datapath Control Datapath Memory Processor Input Output Abstract View of our single cycle processor ° looks like a FSM with PC as state PC Next PC Register Fetch ALU Reg. Wrt Mem Access Data Mem Instruction Fetch Result Store ALUctr RegDst ALUSrc ExtOp MemWr Equal nPC_sel RegWr MemWr MemRd Main Control ALU control op fun Ext What’s wrong with our CPI=1 processor? ° Long Cycle Time ° All instructions take as much time as the slowest ° Real memory is not as nice as our idealized memory • cannot always get the job done in one (short) cycle PC Inst Memory mux ALU Data Mem mux PC Reg File Inst Memory mux ALU mux PC Inst Memory mux ALU Data Mem PC Inst Memory cmp mux Reg File Reg File Reg File Arithmetic & Logical Load Store Branch Critical Path setup setup Reducing Cycle Time ° Cut combinational dependency graph and insert register / latch ° Do same work in two fast cycles, rather than one slow one ° May be able to short-circuit path and remove some components for some instructions! storage element Acyclic Combinational Logic storage element storage element Acyclic Combinational Logic (A) storage element storage element Acyclic Combinational Logic (B) ⇒ Basic Limits on Cycle Time ° Next address logic • PC <= branch ? PC + offset : PC + 4 ° Instruction Fetch • InstructionReg <= Mem[PC] ° Register Access • A <= R[rs] ° ALU operation • R <= A + B PC Next PC Operand Fetch Exec Reg. File Mem Access Data Mem Instruction Fetch Result Store ALUctr RegDst ALUSrc ExtOp MemWr nPC_sel RegWr MemWr MemRd Control Partitioning the CPI=1 Datapath ° Add registers between smallest steps ° Place enables on all registers PC Next PC Operand Fetch Exec Reg. File Mem Access Data Mem Instruction Fetch Result Store ALUctr RegDst ALUSrc ExtOp MemWr nPC_sel RegWr MemWr MemRd Equal Example Multicycle Datapath ° Critical Path ?...
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This note was uploaded on 03/23/2011 for the course CPSC 321 taught by Professor Staff during the Spring '08 term at Texas A&M.

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slide10 - CPSC 321 Computer Architecture and Engineering...

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