slide12 - Pipelining - II Adapted from CS 152C (UC...

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Pipelining - II Adapted from CS 152C (UC Berkeley) lectures notes of Spring 2002
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Revisiting Pipelining Lessons Pipelining doesn’t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously using different resources Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to “fill” pipeline and time to “drain” it reduces speedup Stall for Dependences A B C D 6 PM 7 8 9 T a s k O r d e r Time 30 40 40 40 40 20
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Structural Hazards Hardware design Control Hazard Decision based on results Data Hazard Data Dependency Revisiting Pipelining Hazards
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Control Signals for existing Datapath The Right to Left Control can lead to hazards M U X P C ADD Registers ADD ADD Sign Extend 4 Instruction Memory Address Instruction Read Reg1 Read Reg2 Write Reg Write Data Read Data1 Read Data2 M U X Data Memory Address Write Data Read Data M U X IF: Instruction Fetch ID: Instruction Decode / register file read EX: Execute/address calculation MEM: Memory Access WB: Write back 16 32 Shift left 2 Zero
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Place registers between each step M U X P C ADD Registers ADD ADD Sign Extend 4 Instruction Memory Address Instruction Read Reg1 Read Reg2 Write Reg Write Data Read Data1 Read Data2 M U X Data Memory Address Write Data Read Data M U X 16 32 Shift left 2 Zero IF/ID ID/EX EX/MEM MEM/WB
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Example 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15
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Start: Fetch 10 Exec Reg. File Mem Access Data A B S Reg IR Inst. Mem D Decode Mem Ctrl WB Ctrl M rs rt im 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 IF PC Next PC 10 = n n n n
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Fetch 14, Decode 10 Exec Reg. File Mem Access Data A B S Reg IR Inst. Mem D Decode Mem Ctrl WB Ctrl M 2 rt im 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 lw r1, r2(35) ID IF PC Next PC 14 = n n n
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Fetch 20, Decode 14, Exec 10 Exec Reg. File Mem Access Data r2 B S Reg IR Inst. Mem D Decode Mem Ctrl WB Ctrl M 2 rt 35 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 lw r1 addI r2, r2, 3 EX PC Next PC 20 = n n
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Fetch 24, Decode 20, Exec 14, Mem 10 Exec Reg. File Mem Access Data r2 B r2+35 Reg IR Inst. Mem D Decode Mem Ctrl WB Ctrl M 4 5 3 10 lw r1, r2(35) 14 addI r2, r2, 3 20 sub r3, r4, r5 24 beq r6, r7, 100 30 ori r8, r9, 17 34 add r10, r11, r12 100 and r13, r14, 15 lw r1 sub r3, r4, r5 addI r2, r2, 3 ID IF EX M PC Next PC 24 = n
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slide12 - Pipelining - II Adapted from CS 152C (UC...

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