slide13 - Memory Subsystem and Cache Adapted from lectures...

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Memory Subsystem and Cache Adapted from lectures notes of Dr. Patterson and Dr. Kubiatowicz of UC Berkeley
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The Big Picture Control Datapath Memory Processor Input Output
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Technology Trends DRAM Year Size Cycle Time 1980 64 Kb 250 ns 1983 256 Kb 220 ns 1986 1 Mb 190 ns 1989 4 Mb 165 ns 1992 16 Mb 145 ns 1995 64 Mb 120 ns Capacity Speed (latency) Logic: 2x in 3 years 2x in 3 years DRAM: 4x in 3 years 2x in 10 years Disk: 4x in 3 years 2x in 10 years 1000:1! 2:1!
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Technology Trends [contd…] µProc 60%/yr. (2X/1.5yr) DRAM 9%/yr. (2X/10 yrs) 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Time “Moore’s Law” Processor-DRAM Memory Gap (latency) “Less’ Law?”
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The Goal: Large, Fast, Cheap Memory !!! Fact Large memories are slow Fast memories are small How do we create a memory that is large, cheap and fast (most of the time) ? Hierarchy Parallelism
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By taking advantage of the principle of locality: Present the user with as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology. Control Datapath Secondary Storage (Disk) Processor Registers Main Memory (DRAM) Second Level Cache (SRAM) On-Chip Cache 1s 10,000,000 ns (10 ms) Speed (ns): 10ns 100ns 100s Gs Size (bytes): Ks Ms Tertiary Storage (Tape) 10,000,000,000ns (10 sec) Ts
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Today’s Situation Rely on caches to bridge gap Microprocessor-DRAM performance gap time of a full cache miss in instructions executed 1st Alpha (7000): 340 ns/5.0 ns = 68 clks x 2 or 136 instructions 2nd Alpha (8400): 266 ns/3.3 ns = 80 clks x 4 or 320 instructions
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Memory Hierarchy (1/4) Processor executes programs runs on order of nanoseconds to picoseconds needs to access code and data for programs: where are these? Disk HUGE capacity (virtually limitless) VERY slow: runs on order of milliseconds so how do we account for this gap?
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Memory Hierarchy (2/4) Memory (DRAM) smaller than disk (not limitless capacity) contains subset of data on disk: basically portions of programs that are currently being run much faster than disk: memory accesses don’t slow down processor quite as much Problem: memory is still too slow (hundreds of nanoseconds) Solution: add more layers ( caches )
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Memory Hierarchy (3/4) Processor Size of memory at each level Increasing Distance from Proc., Decreasing cost / MB Level 1 Level 2 Level n Level 3 . . . Higher Lower Levels in memory hierarchy
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Memory Hierarchy (4/4) If level is closer to Processor, it must be: smaller faster subset of all higher levels (contains most recently used data) contain at least all the data in all lower levels Lowest Level (usually disk) contains all available data
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Analogy: Library You’re writing a term paper (Processor) at a table in Evans Evans Library is equivalent to disk essentially limitless capacity
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This note was uploaded on 03/23/2011 for the course CPSC 321 taught by Professor Staff during the Spring '08 term at Texas A&M.

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slide13 - Memory Subsystem and Cache Adapted from lectures...

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