slide14 - Cache Memory Adapted from lectures notes of Dr....

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Cache Memory Adapted from lectures notes of Dr. Patterson and Dr. Kubiatowicz of UC Berkeley
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Revisiting Memory Hierarchy Facts Big is slow Fast is small Increase performance by having “hierarchy” of memory subsystems “Temporal Locality” and “Spatial Locality” are big ideas
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Revisiting Memory Hierarchy Terms Cache Miss Cache Hit Hit Rate Miss Rate Index, Offset and Tag
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Direct Mapped Cache
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Direct Mapped Cache [contd…] What is the size of cache ? 4K If I read 0000 0000 0000 0000 0000 0000 1000 0001 What is the index number checked ? 32 If the number was found, what are the inputs to comparator ?
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Direct Mapped Cache [contd…] Taking advantage of spatial locality, we read 4 bytes at a time
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Direct Mapped Cache [contd…] Advantage Simple Fast Disadvantage Mapping is fixed !!!
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Associative Caches Block 12 placed in 8 block cache: Fully associative, direct mapped, 2-way set associative S.A. Mapping = Block Number Modulo Number Sets 0 1 2 3 4 5 6 7 Block no. Fully associative: block 12 can go anywhere 0 1 2 3 4 5 6 7 Block no. Direct mapped: block 12 can go only into block 4 (12 mod 8) 0 1 2 3 4 5 6 7 Block no. Set associative: block 12 can go anywhere in set 0 (12 mod 4) Set 0 Set 1 Set 2 Set 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 Block-frame address 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 Block no.
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Set Associative Cache N-way set associative : N entries for each Cache Index N direct mapped caches operates in parallel Example: Two-way set associative cache Cache Index selects a “set” from the cache The two tags in the set are compared to the input in parallel Data is selected based on the tag result Cache Data Cache Block 0 Cache Tag Valid : : : Cache Data Cache Block 0 Cache Tag Valid : : : Cache Index Mux 0 1 Sel1 Sel0 Cache Block Compare Adr Tag Compare OR Hit
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Example: 4-way set associative Cache What is the cache size in this case ?
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Disadvantages of Set Associative Cache N-way Set Associative Cache versus Direct Mapped Cache: N comparators vs. 1 Extra MUX delay for the data Data comes AFTER Hit/Miss decision and set selection In a direct mapped cache, Cache Block is available BEFORE Hit/Miss: Cache Data Cache Block 0 Cache Tag Valid : : : Cache Data
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slide14 - Cache Memory Adapted from lectures notes of Dr....

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