w9-four

w9-four - Where are we now? 198:211 Computer Architecture...

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1 1 198:211 Computer Architecture z Topics: z Processor Design 2 Where are we now? z C-Programming z A “real” computer language… z Data Representation z Everything goes down to bits and bytes z Machine representation Language z Very limited programming model z Digital Logic z Transistors J Gates J Circuits z Circuits J { Memory, Registers, and Components} z What are we going to do now…. 3 Processor Design z Figure out how a small subset of the instruction set works in hardware z Use Hardware blocks to describe data path z Use control logic to ensure steps of the instruction flows smoothly 4 Add instruction z Type of add depends on where operands are located z add reg1, reg2 z Add contents of reg1 to reg2 and store result in reg2 z add $constant, reg2 z Add contents of memory immediately following the instruction to reg 2 and store result in reg2 z add (effective-address), reg2 z Add contents of effective address to reg2 and store result in reg2 z Effective address could be relative; relative + offset; relative + offset, index; relative + offset, index*scaled
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2 5 Instruction Example z Addition Instruction z Add value in register %edx to that in register %eax z Store result in register %eax z Two-byte encoding z First indicates instruction type z Second gives source and destination registers addl %edx , %eax 0 3 rA rB Encoded Representation Generic Form 6 ADD-Add : note src, dst are reversed in the intel manual In assembly language add src, dst means src + dst Æ dst 7 8 Instruction Example in x86 z Addition Instruction z Opcode is 03 and src, dst are %edx, %eax z from previous table (Table 2.2) code is C2 z So, 03 C2 means add %edx, %eax z 03 45 z means add 8(%ebp), %eax z 05 z add $cons, %eax addl %edx , %eax 0 3 C 2 Encoded Representation Generic Form addl 8( %ebp) , %eax 0 3 4 5 addl $4, %eax 0 5 000 4
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3 9 Arithmetic and Logical Operations z The second byte will vary based on type of operands z Set condition codes as side effect subl rA , rB 2 B rA rB andl rA , rB 2 3 rA rB xorl rA , rB 3 3 rA rB Subtract (rA from rB) And Exclusive-Or Instruction Code Function Code Lower 4 bits can vary 30 means 8 byte register transfer, Lower 4 bits can vary depending upon the type Of operand 20 means 8 byte register transfer, 10 Subtract operation- Instruction Set Reference 11 12
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This note was uploaded on 03/24/2011 for the course CS 211 taught by Professor Chakraborty during the Spring '08 term at Rutgers.

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w9-four - Where are we now? 198:211 Computer Architecture...

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