w11-a-one-caches

w11-a-one-caches - Direct-Mapped Cache Simulation t=1 s=2 x...

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1 Direct-Mapped Cache Simulation M=16 bit addresses, B=2 bytes/block, S=4 sets, E=1 entry/set Address trace (reads): 0 [0000 2 ], 1 [0001 2 ], 13 [1101 2 ], 8 [1000 2 ], 0 [0000 2 ] x t=1 s=2 b=1 xx x 1 0 m[1] m[0] v tag data 0 [0000 2 ] (miss) (1) 1 0 m[1] m[0] v tag data 1 1 m[13] m[12] 13 [1101 2 ] (miss) (3) 1 1 m[9] m[8] v tag data 8 [1000 2 ] (miss) (4) 1 0 m[1] m[0] v tag data 1 1 m[13] m[12] 0 [0000 2 ] (miss) (5) 0 M[0-1] 1 1 M[12-13] 1 1 M[8-9] 1 1 M[12-13] 1 0 M[0-1] 1 1 M[12-13] 1 0 M[0-1] 1
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2 Why Use Middle Bits as Index? z High-Order Bit Indexing z Adjacent memory lines would map to same cache entry z Poor use of spatial locality z Middle-Order Bit Indexing z Consecutive memory lines map to different cache lines z Can hold C-byte region of address space in cache at one time 4-line Cache High-Order Bit Indexing Middle-Order Bit Indexing 00 01 10 11 00 00 00 01 00 10 00 11 01 00 01 01 01 10 01 11 10 00 10 01 10 10 10 11 11 00 11 01 11 10 11 11 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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3 Set Associative Caches z Characterized by more than one line per set valid tag set 0: E=2 lines per set set 1: set S-1: ••• cache block valid tag cache block valid tag cache block valid tag cache block valid tag cache block valid tag cache block
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4 Accessing Set Associative Caches z Set selection z identical to direct-mapped cache valid valid tag tag set 0: valid valid tag tag set 1: valid valid tag tag set S-1: ••• t bits s bits 0 0 0 0 1 0 m-1 b bits tag set index block offset Selected set cache block cache block cache block cache block cache block cache block
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5 Accessing Set Associative Caches z Line matching and word selection z must compare the tag in each valid line in the selected set. 1 0110 w 3 w 0 w 1 w 2 1 1001 t bits s bits 100 i 0110 0 m-1 b bits tag set index block offset selected set (i): =1? (1) The valid bit must be set. = ? (2) The tag bits in one of the cache lines must match the tag bits in the address (3) If (1) and (2), then cache hit, and block offset selects starting byte. 3 01 2 7 45 6
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6 Accessing Set Associative Caches z Line matching and word selection z must compare the tag in each valid line in the selected set. 1 0110 w 3 w 0 w 1 w 2 1 1001 t bits s bits 100 i 0110 0 m-1 b bits tag set index block offset selected set (i): =1? (1) The valid bit must be set. = ? (2) The tag bits in one of the cache lines must match the tag bits in the address (3) If (1) and (2), then cache hit, and block offset selects starting byte.
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This note was uploaded on 03/24/2011 for the course CS 211 taught by Professor Chakraborty during the Spring '08 term at Rutgers.

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w11-a-one-caches - Direct-Mapped Cache Simulation t=1 s=2 x...

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