w11-one-caches

w11-one-caches - CS211 Computer Architecture The Memory...

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1 The Memory Hierarchy z Topics z Storage technologies and trends z Locality of reference z Caching in the memory hierarchy CS211 Computer Architecture
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2 Memory until now… z We’ve relied on a very simple model of memory for most this class z Main Memory is a linear array of bytes that can be accessed given a memory address z Also used registers to store values z Reality is more complex. There is an entire memory system. z Different memories exist at different levels of the computer z Each vary in their speed, size, and cost
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3 Random-Access Memory (RAM) z Key features z RAM is packaged as a chip. z Basic storage unit is a cell (one bit per cell). z Multiple RAM chips form a memory. z Static RAM ( SRAM ) z Each cell stores bit with a six-transistor circuit. z Retains value indefinitely, as long as it is kept powered. z Relatively insensitive to disturbances such as electrical noise. z Faster and more expensive than DRAM. z Dynamic RAM ( DRAM ) z Each cell stores bit with a capacitor and transistor. z Value must be refreshed every 10-100 ms. z Sensitive to disturbances. z Slower and cheaper than SRAM.
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4 Memory speeds z Processor Speeds : 1 GHz processor speed is 1 nsec cycle time. z Memory Speeds (50 nsec) DIMM Module Chip Type Clock Speed[MHz] Bus Speed[ MHz] Transfer Rate [MB/s] PC1600 DDR200 100 200 1,600 PC2100 DDR266 133 266 2,133 PC2400 DDR300 150 300 2,400 z Access Speed gap z Instructions that store or load from memory
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5 Conventional DRAM Organization z d x w DRAM: z dw total bits organized as d supercells of size w bits cols rows 0 123 0 1 2 3 internal row buffer 16 x 8 DRAM chip addr data supercell (2,1) 4 bits / 8 bits / memory controller (to CPU)
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6 Reading DRAM Supercell (2,1) z Step 1(a): Row access strobe ( RAS ) selects row 2. cols rows RAS = 2 0 123 0 1 2 internal row buffer 16 x 8 DRAM chip 3 addr data 2 / 8 / memory controller z Step 1(b): Row 2 copied from DRAM array to row buffer.
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7 Reading DRAM Supercell (2,1) z Step 2(a): Column access strobe ( CAS ) selects column 1. cols rows 0 123 0 1 2 3 internal row buffer 16 x 8 DRAM chip CAS = 1 addr data 2 / 8 / memory controller z Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU. supercell (2,1) supercell (2,1) To CPU
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8 Memory Modules… real life z We’ve only been discussing single DRAM Chips z Several DRAM chips are bundled into Memory Modules z SIMMS - Single Inline Memory Module z DIMMS - Dual Inline Memory Module Source for Pictures: http://en.kioskea.net/contents/pc/ram.php3
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9 Von Neumann Main
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w11-one-caches - CS211 Computer Architecture The Memory...

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