w14-one-Buses

w14-one-Buses - 198:211 Computer Architecture Topics System...

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1 198:211 Computer Architecture z Topics: z System I/O z Buses
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2 I/O or input and output z In addition to memory, data transfer needs to occur between CPU and Input output devices z When reading from memory, a byte or several bytes can be transferred from memory to register using z mov address, %eax or mov %eax, address z I/O devices also are sources or destinations for bytes of data z I/O devices can be viewed just as memory z I/O devices can be viewed as separate from memory
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3 I/O programming z There are two ways of addressing I/O devices z Memory mapped I/O z The address space is divided between memory and I/O devices z Higher order addresses can refer to device z Lower order addresses can refer to memory z mov %eax, address will fetch data from I/O or memory based on the address z E.g., memory range to from 0000 to BFFF z I/O range from C000 to CFFF z Device or memory selection based on address range z Different devices can have different addresses in the I/O range
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4 Memory mapped I/O z Send or receive data to /from I/O device is a memory transfer instruction (mov) with the right address z Main memory not selected when address is in I/O range z Adv z Uniformity of programming, same mov works for I/O and memory z Dis adv z Memory address space is reduced CPU Memory - I/O Bus Main Memory keyboard Disk Display Network
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5 I/O mapped I/O z Memory and I/O devices use distinct address spaces z Isolated I/O z Two separate instructions to address I/O devices z A separate code or control signal based on the op code will select memory or I/O z IN for input z OUT for output z mov for memory access z Less flexible for programming 0000 FFFF 00FF 0000 I/O MEM
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8 Interfacing with I/O z Many devices, with varying speeds, complexity z CPU/bus shared among all peripherals and memory z CPU should be able to select a device and transfer data
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w14-one-Buses - 198:211 Computer Architecture Topics System...

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