Tutorial 5

Tutorial 5 - Elec 151 Tutorial #5 Outline: Lab 5:...

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Elec151 - Tutorial 5 1 Outline: Lab 5: Flip-Flops and Sequential Logic I • Clock Generator using 555 timer IC • Latch vs Flip-flop – Types: SR, JK, D, T • Converting from one type of flip-flop to another: Examples Elec 151 Tutorial #5 ELEC151 - Tutorial 5 2 Clock Generator using 555 timer IC 555 Timer Output T1 = Clock high time =0 . 7 (R a +R b )C 1 T2 = Clock low time . 7 b 1 T = Clock period = T1 +T2 .7(R a +2R b 1 DC = Duty cycle = T1/T == period time high RR ab + + 2 0 1 T1 T2 T Clk Bypass capacitor 74LS14 .01μF Elec151 - Tutorial 5 3 D Q Q C D Q = + 2 Q Latch (level-sensitive) vs Flip-Flops (edge-triggered) Level-sensitive latch output (Q A ): Q A follows D as long as Clk=1 • Positive edge-triggered flip-flop output (Q B ): Q B takes value of D sampled during Clk transition from 0 to 1 0 1 0 1 0 1 time Clk D Q A Q B 0 1 Positive level sensitive D latch Positive edge-triggered D Flip-flop Q A Q B D Q Q C Elec151 - Tutorial 5 4 SR Types Q R S Q + = + R Q Q C S R Q Q C S + Q S 0 0 1 R 0 1 1 0 Q 0 X 1 Hold Reset Set Not allowed Q R S Q + = + + Q R 0 0 S 0 0 1 1 0 Q 0 1 1 0 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 1 1 X X Hold Reset Set Not allowed Proof: Q SR 0 1 00 01 11 10 1 0 X X 0 0
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This note was uploaded on 03/27/2011 for the course ELEC 151 taught by Professor Cy during the Spring '10 term at HKUST.

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Tutorial 5 - Elec 151 Tutorial #5 Outline: Lab 5:...

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