Tutorial 6

Tutorial 6 - Elec 151 Tutorial #6 Outline: •...

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Unformatted text preview: Elec 151 Tutorial #6 Outline: • Combinational Logic (multi-level logic) - Inverter to NAND/NOR gate - Push Bubble - AOI and OAI - Problems Combinational Logic (multi-level logic) Inverter to NAND & NOR gates x Out <> Push Bubble x y Out x Out <> x Out x <> Out Out x y x y <> Out y • Multiplexers & Demultiplexers - Problems 1 x y <> Out <> x y Out Elec151 - Tutorial #6 Elec151 - Tutorial #6 2 AOI (AND-OR-Invert) and OAI (OR-AND-Invert) 2x2 AOI … AOI (AND-OR-Invert) and OAI (OR-AND-Invert) 3x2 AOI or 3-3 AOI 2 stack A B C D 2x3 OAI & & <> + & + 3x2 AOI Z <> & 2x2 AOI 3-2-2-3 AOI (e.g. 74LS54 3-2-2-3 Input (4-stack) AND-O-INVERT Gate) 4 stack A B C D E F + Z & <> +& + 2x3 OAI 3 <> & + & & 3-2-2-3 AOI Elec151 - Tutorial #6 Elec151 - Tutorial #6 4 1. PROB Represent: F = AB + CD + BD (ii) Using 2-inputs NAND gates • i) Using 2-inputs AND and OR gates • ii) Using 2-inputs NAND gates only • iii) Using 2-inputs NOR gates only • iv) Using 2x2 AOI gates only i) Using 2-inputs AND and OR gates A B C D B D F <> A B C D B D F A B C D B D RTT F <> A B C D <> F A B C D B D <> F A B C D B D F B D Elec151 - Tutorial #6 5 Elec151 - Tutorial #6 6 (iii) Using 2-inputs NOR gates (iv) Using 2x2 AOI gates __ The trick is to rearrange the expression to the form: (M1N1 + O1P1) . (M2N2 + O2P2) + ………….. A B C D B D __ F <> A __ B __ C __ D __ F B __ D __ M N O & & + F F = AB + CD + BD = AB + CD + BD + (0)(0) = AB + CD + P <> A __ B __ C __ D __ <> A __ B __ C __ D __ F = MN + OP F [ ] [ BD + (0)(0) ] = [ AB + CD ]• [ BD + (0)(0) ] [ ][ BD + (0)(0) + (0 )(0 ) B __ D __ B __ D __ __ __ = AB + CD • D D 7 where A A B B C C Elec151 - Tutorial #6 Elec151 - Tutorial #6 8 … continue … Using 2x2 AOI gates 3. PROB F = AB + CD • [ [ & BD + (0)(0) + (0 )(0 ) Draw the schematic for the following expression, mapped into NAND-only network. Assume that literals and their complements are available. A B C D A B C+ AC + A B __ __ __ __ + & 0 0 & + & F Solution A __ B __ C __ Note: AND-OR array = NAND-NAND <> B D & + & A C __ 0 0 A B <> RTT Elec151 - Tutorial #6 9 Elec151 - Tutorial #6 10 4. PROB Draw the schematic for the following expression, mapped into NAND-only network. Assume that literals and their complements are available. Multiplexers & Demultiplexers Multiplexer (Selector) 4:1 Multiplexer 8:1 Multiplexer In 0 In 1 In 2 In 3 In 4 In 5 In 6 In 7 000 001 010 011 100 101 110 ( A+ B + C ) ( A+ B ) ( A+ C ) __ __ __ __ __ __ __ Solution __ 2:1 Multiplexer A __ B __ C __ A __ B __ A __ C <> A B C A B A C In 0 In 1 0 2 : 1 Out MUX 1 S0 S0 0 1 00 4 : 1 In 1 01 MUX Out In 2 10 In 3 11 S1 S 0 S1 S0 00 01 0 11 In 0 8 :1 MUX Out 111 S 2 S1 S 0 Out In 0 In 1 In 2 In 3 Elec151 - Tutorial #6 S 2 S1 S 0 000 001 . . . Out In 0 In 1 Out In 0 In 1 111 In 7 12 Elec151 - Tutorial #6 11 Demultiplexer / Decoder 1:2 DEMUX 2:4 DEMUX 2:4 DEC (2-Input Binary Decoder) 8. PROB A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Implement a circuit that performs the truth table shown below using: • (i) 16:1 MUX (ii) 8:1 MUX and 2:1 MUX In 1 : 2 DEMUX 0 Out 0 1 Out1 00 Out 0 In DEMUX 10 Out 2 11 Out 3 S1 S 0 2 : 4 01 Out 1 Enable E 00 Out 0 DEC 2 : 4 01 Out 1 10 Out 2 S0 S0 0 1 Out 0 Out 1 In 0 In 0 11 Out 3 S1 S 0 S1 S0 E 001 011 01 111 Out 0 Out 1 Out 2 Out 3 S1 S0 00 01 0 11 Out 0 Out 1 Out 2 Out 3 In 0 0 0 In 0 0 0 In 0 0 0 In 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 See: A decoder is a demultiplexer with In = Enable =1 ! RTT Elec151 - Tutorial #6 CD 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 • • • • • • • • • • (iii) 8:1 MUX controlled by inputs B,C,A and 2:1 MUX by input D. (iv) 8:1 MUX (v) 8:1 MUX controlled by inputs B,C,D. (vi) 4:1 MUX (vii)One 4:1 MUX and any gate (viii) 4:16 DEMUX and OR gate (ix) 4:16 DEC and OR gate (x) 4:16 DEMUX and NAND gate (xi) One 4:1 MUX controlled by A and B, a 2:4 DEC controlled by C and D and 3 OR gates (xii) Any gate Elec151 - Tutorial #6 13 14 Solution (i) Using 16:1 MUX In 0 In 1 In 2 In 3 In 4 In 5 In 6 In 7 In 8 In 9 In 10 In 11 In 12 In 13 In 14 In 15 (i) … Using 16:1 MUX 16:1 MUX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S3 S 2 S1 S0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 1 0 0 1 0 0 Z 1 0 0 1 Z In 0 In 1 In 2 In 3 In 4 In 5 In 6 In 7 In 8 In 9 In 10 In 11 In 12 In 13 In 14 In 15 A BCD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 16:1 MUX 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 Z 1 0 0 1 S3 S 2 S1 S0 Elec151 - Tutorial #6 ABC 15 Elec151 - Tutorial #6 D 16 (ii) Using 8:1 MUX and 2:1 MUX A BCD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 8:1 MUX (iii) Using 8:1 MUX controlled by inputs B,C,A and 2:1 MUX by input D A BCD Z 000 1 001 0 0 01 011 0 100 0 101 0 1 01 111 1 000 1 001 0 0 0 0 011 0 100 1 101 1 0 1 0 111 0 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 1 B C 0 1 0 1 0 1 0 1 D BC A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 00 0 10 00 00 0 10 01 01 1 11 01 01 1 11 2:1 MUX 0 Z D 0 0 0 1 0 1 0 1 0 1 1 A 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 DBCA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Z 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 1 00 01 0 11 00 01 0 11 0 Z BCA 0 0 0 0 0 1 1 0 1 1 00 01 0 11 00 01 0 11 D BC A 1 B C D RTT Elec151 - Tutorial #6 17 Elec151 - Tutorial #6 18 (iv) Using 8:1 MUX A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CD 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 (v) … Using 8:1 MUX controlled by inputs B, C, D A BCD Z 000 1 001 0 0 0 1 011 0 100 0 101 0 1 0 1 111 1 000 1 001 0 0 0 0 011 0 100 1 101 1 0 1 0 111 0 BC D A Z 000 1 010 0 00 1 110 0 000 0 01 0 0 00 1 110 1 001 1 011 0 01 0 111 0 001 1 011 1 01 0 111 0 B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DA 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 D D 8:1 MUX 0 1 D D D 0 1 D 0 1 0 0 0 0 0 1 1 1 1 A 0 0 1 0 0 1 B 0 1 0 1 0 1 0 1 Z C 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Z 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 0 _ 8:1 MUX A 0 1 0 A 0 A A _ A A A A 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 Z A _ BCD A Elec151 - Tutorial #6 19 Elec151 - Tutorial #6 20 (vi) Using 4:1 MUX 4:1 MUX (vii) One 4:1 MUX and any gate ABCD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RTT 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 C 0 0 1 D 0 1 0 1 ABCD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 21 0 0 1 1 C 0 0 1 D 0 1 0 1 0 0 1 0 1 0 1 Z 1 0 0 0 C 0 0 1 D 0 1 0 1 AB 1 1 0 0 C 0 0 1 D 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 _ D C 4:1 MUX 0 0 0 1 0 1 Z 1 _ C _ AB D _ C Elec151 - Tutorial #6 Elec151 - Tutorial #6 22 (viii) Using 4:16 DEMUX and OR gate A BCD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 (ix) Using 4:16 DEC and OR gate A BCD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 4:16 DEMUX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 In = 1 1 0 0 1 0 0 Z 1 0 0 1 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 4:16 Decoder 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 E =1 1 0 0 1 0 0 Z E = Enable 1 0 0 1 Note: A decoder is a demultiplexer with In = Enable =1 24 ABC D 23 ABC D Elec151 - Tutorial #6 Elec151 - Tutorial #6 (x) Using 4:16 DEMUX and NAND gate 4:16 DEMUX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 4:16 DEMUX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Out 0 Out 1 Z Z In=1 In=1 Out 15 ABCD ABCD Notes: 1. AND-OR Array = NAND-NAND array 2. The DEMUX shown to the right: Out = 0 when selected, Out = H when not selected (e.g. For ABCD=1111 => Out15 = 0, Out 0 to Out 14 = H) RTT Elec151 - Tutorial #6 (xi) One 4:1 MUX, a 2:4 DEC and 3 OR gates (A and B for MUX inputs, C and D for DEC inputs) ABCD Z 0000 1 0001 0 00 0 1 0011 0 00 0100 0 0101 0 2 : 4 01 In = 1 DEC 01 0 1 10 0111 1 1000 1 11 1001 0 10 0 0 CD 1011 0 1100 1 1101 1 0 11 0 1111 0 Elec151 - Tutorial #6 4:1 MUX 0 0 0 1 0 1 Z 1 AB 25 26 (xii) Using any gate A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CD 00 01 0 11 00 01 0 11 00 01 0 11 00 01 0 11 Z 1 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 Directly from the truth table! Z = A B C D+ A B C D+ A BC D+ A BCD + A B C D+ AB C D+ AB C D ____ __ _ _ _ _ ___ __ _ That’s all Folks! Study Hard!! Elec151 - Tutorial #6 27 Elec151 - Tutorial #6 28 ...
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