Lecture 3- Logic ï¼­inimization

Lecture 3- Logic ï¼­inimization...

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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 1 Lecture 3a Gate Level Minimization ELEC151 Digital Circuits and Systems Spring 2011 Instructor: Levent Yobas
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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 2 Lecture Overview Two-level logic minimization K-map method Other methods of logic minimization Reading assignment: Chapter 3.1 to 3.6
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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 3 Boolean Algebra & Logic Circuits
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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 4 Example – Full Adder Design Specifications – calculating 1-bit of binary addition Add two binary digits and Carry in to produce Sum and Carry outE.g. A B Cin Sum Cout 000 0 0 001 1 0 010 1 0 011 0 1 100 1 0 101 0 1 110 0 1 111 1 1 Boolean Expression (Canonical Form, Sum of Minterms) Sum = A ' B ' C in + A ' BC in ' + AB ' C in ' + ABC in C out = A ' BC in + AB ' C in + ABC in ' + ABC in
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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 5 Example – Full Adder Design Boolean expression simplification C out = A ' BC in + AB ' C in + ABC in ' + ABC in = A ' BC in + AB ' C in + ABC in ' + ABC in + ABC in = A ' BC in + ABC in + AB ' C in + ABC in ' + ABC in = ( A ' + A ) BC in + AB ' C in + ABC in ' + ABC in = BC in + AB ' C in + ABC in ' + ABC in + ABC in = BC in + AB ' C in + ABC in + ABC in ' + ABC in = BC in + A ( B ' + B ) C in + ABC in ' + ABC in = BC in + AC in + AB ( C in ' + C in ) = BC in + AC in + AB Sum = A ' B ' C in + A ' BC in ' + AB ' C in ' + ABC in = Identity Associative distributive Identity Associative distributive distributive complement
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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 6 Example – Full Adder Design Implementation C out = A ' BC in + AB ' C in + ABC in ' + ABC in = BC in + AC in + AB Sum = A ' B ' C in + A ' BC in ' + AB ' C in ' + ABC in =
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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 7 Karnaugh Map Method Truth table and Karnaugh Map (K-Map) Truth table: input/output relation in one-dimensional table K map: input/output relation in two-dimensional graph K-map helps visualize adjacencies in up to 6 variables but it is hard to draw cubes of more than 4 variables Beyond that, computer-based methods are needed Adjacency is arranged in 2-bit Gray code sequence 00, 01, 11, 10 only one-bit change from one code word to the next code word A B 0 1 0 1 0 1 2 3 0 1 2 3 6 7 4 5 AB C 00 01 11 10 0 1 2- variable K-map 3- variable K-map In the K-map, adjacency wraps from left to right and from top to bottom B
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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 8 Alternative K-Map Expressions 3-variable truth table and K-Maps m 1 m 2 m 3 m 4 m 5 m 6 m 7 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Minterms m 0 0 1 2 3 6 7 4 5 AB C A B 00 01 11 10 0 1 0 4 1 5 3 7 2 6 BC A B C 00 01 11 10 0 1 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 AB CD 00 01 11 10 00 01 10 C B D 0 4 12 8 1 5 13 9 3 7 15 2 6 14 10 CD AB 00 01 11 10 00 01 10 C B D 4- variable K-map There is an equal opportunity to use either expression. The textbook uses the right one
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ELEC151 Spring 2011 – L. Yobas Lecture 3 – 9 Logic Minimization using K-Map F = A . B + A . B = A ( B + B ) ABF 000 010 101 111 0 1 1 0 A A B B A F = 0 1 1 0 A A B B Logic minimization (2 AND gates, 1 OR gate to a wire) Circle as many ones as we can with one circle.
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Lecture 3- Logic ï¼­inimization...

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