Lecture 5- VHDL

Lecture 5- VHDL - ELEC151 Spring 2011 L.Yobas Lecture 5 1...

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ELEC151 Spring 2011 – L. Yobas Lecture 5 – 1 Lecture 5 Introduction to VHDL ELEC151 Digital Circuits and Systems Spring 2011 Instructor: Levent Yobas
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ELEC151 Spring 2011 – L. Yobas Lecture 5 – 2 Lecture Overview VHDL for Combinational circuits Reading Assignments: Chapter 4.8-4.9
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ELEC151 Spring 2011 – L. Yobas Lecture 5 – 3 Digital System Description There are many ways to describe a digital system Schematic diagram Pictorial representation of structure State diagram Diagram showing sequence of operations (for sequential circuits), we will cover this when we discuss sequential logic Te x t Specific text format to describe the view of a system Similar to computer language, program Can handle large number of device and large circuit size/complexity
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ELEC151 Spring 2011 – L. Yobas Lecture 5 – 4 Hardware Description Language (HDL) A Language for us to describe a hardware without actually physically designing the hardware first. Use as specification, documentation, modelling Can be used for synthesis and verification Synthesis Using computer software (CAD software) to generate the circuit from the description of the hardware Verification Using computer software (simulation) to verify your design before you actually build it Two common HDL –Verilog and VHDL, we will learn VHDL in this course VHDL stands for VHSIC (very high speed IC) Hardware Description Language Become IEEE standard in 1987, revised in 1993
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ELEC151 Spring 2011 – L. Yobas Lecture 5 – 5 Abstraction level of a system A digital system can be described at different levels Behavioral Level Describe the functions (behavior) of the system without giving any implementation details Does not tell what hardware (e.g. gates) are used to implement the function Data flow level Give the Boolean logic equation of the system Structural level Specify the gates (hardware modules) that are used to implement the function Also specify the interconnection of the gates (or devices) that implementing the function VHDL is a language that can help us to describe the system in different levels of abstraction
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ELEC151 Spring 2011 – L. Yobas Lecture 5 – 6 AN adder example Behavior view: F = A+B Dataflow view C 1 = A 0 B 0 +A 0 C 0 +B 0 C 0 S 1 = A 0 (B 0 )’(C 0 )’ +(A 0 )’B 0 (C 0 )’ + (A 0 )’(B 0 )’ C 0 +A 0 B 0 C 0 Structural view
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Lecture 5 – 7 VHDL Basic Concept A given circuit is presented as a Design Entity A design entity consists of two descriptions: an input/output interface description and one or more architectural bodies entity ONES_CNT is port (A: in std_logic_vector(2 downto 0); C: out std_logic_vector(1 downto 0)); end ONES_CNT; ENTITY component_name IS input and output ports physical and other parameters END component_name; ARCHITECTURE identifier OF component_nameIS declarations. BEGIN
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Lecture 5- VHDL - ELEC151 Spring 2011 L.Yobas Lecture 5 1...

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