Introduction to Embedded Microcomputer Systems Lecture 27.1 Jonathan W. Valvano Read Sections 8.2, 9.1, 9.2.1-4, 12.3, 12.4 (Fifo and SCI) Recap Serial communication; what does the frame look like Baud rate vs bandwidth, latency vs real time SCI shift register versus SCI data register How RDRF is set; how RDRF is cleared How TDRE is set; how TDRE is cleared Overview Synchronization: hardware/software, between threads SCI interrupts Fifo queue: what why how What is a Fifo; It is a structured way to pass data Fifo_Putstores data Fifo_Get retreives data First in first out means the data remains in order Source processProducerFIFOorDouble bufferSink processConsumerPutGetFigure 12.4. FIFO queues and double buffers can be used to pass data from a producer to a consumer. Blind Cycle Counting Synchronization Blind cycle counting is appropriate when the I/O delay is fixed and known. This type of synchronization is blind because it provides no feedback from the I/O back to the computer. Gadfly or Busy Waiting Synchronization Check busy/ready flag over and over until it is ready Interrupt Synchronization Request interrupt when busy/ready flag is ready
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