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Sp11 - xxx.lst multiple assembly listing files xxx.map...

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Introduction to Embedded Microcomputer Systems Lecture 21.1 Jonathan W. Valvano Writing embedded systems code in C using Metrowerks Installation Projects Mixed C/assembly PLL Debugger Importing TExaS code from previous labs Exporting object code to simulate in TExaS Installation 9S12/Metrowerks link http://users.ece.utexas.edu/~valvano/S12C32.htm How to download Metrowerks StarterFiles xxxx_DP512.zip is a DP512 Metrowerks project xxxx_DP512asm.zip is a DP512 TExaS example xxxx_DG128.zip is a DG128 Metrowerks project xxxx_DG128asm.zip is a DG128 TExaS example Projects, look at an example starter file, OC_DG128.zip See Folders Sources programs bin object code, TExaS files xxx.mcp project, can double click this Source code files (you create these) (text) xxx.asm assembly source xxx.c C source code file xxx.h C header file Object code files (created when you compile) (text)
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Unformatted text preview: xxx.lst multiple assembly listing files xxx.map symbol table xxx.sx object code Create a new project Add a new file called pll.asm SYNR equ $0034 ; CRG Synthesizer Register REFDV equ $0035 ; CRG Reference Divider Register CRGFLG equ $0037 ; CRG Flags Register CLKSEL equ $0039 ; CRG Clock Select Register PLLCTL equ $003A ; CRG PLL Control Register absentry PLL_Init ;********* PLL_Init **************** ; Active PLL so the 9S12 runs at 24 MHz ; Inputs: none ; Outputs: none ; Errors: will hang if PLL does not stabilize PLL_Init movb #$02,SYNR ; 9S12DP512 OSCCLK is 16 MHz movb #1,REFDV movb #0,CLKSEL ; PLLCLK = 2 * OSCCLK * (SYNR + 1) / (REFDV + 1) movb #$D1,PLLCTL ; Clock monitor, PLL On, high bandwidth filter brclr CRGFLG,#$08,* ; wait for PLLCLK to stabilize. bset CLKSEL,#$80 ; Switch to PLL clock rts Add this to main void PLL_Init(void);...
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