aLec19_timer_threads - Introduction to Embedded...

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Introduction to Embedded Microcomputer Systems Lecture 19.1 Jonathan W. Valvano Recap Parameter passing using the stack LCD programming Fixed-point conversions Overview I/O synchronization Interrupts Output compare periodic interrupts Read Book Sections 9.1, 9.2, 9.4, 9.6.1, 9.6.2 Blind Cycle Counting Synchronization Blind cycle counting is appropriate when the I/O delay is fixed and known. This type of synchronization is blind because it provides no feedback from the I/O back to the computer. Gadfly or Busy Waiting Synchronization Check busy/ready flag over and over until it is ready Interrupt Synchronization Request interrupt when busy/ready flag is ready Synchronizing with an input device Blind Cycle Wait a fixed time Read data Busy-Wait Status Read data Busy Ready Interrupt Fifo Get data from Fifo Empty Ready Read data Put data in Fifo return from interrupt Synchronizing with an output device Blind Cycle Wait a fixed time Write data Busy-Wait Status Write data Busy Ready Interrupt Fifo Put data into Fifo Full Idle Write data Get data from Fifo return from interrupt Fifo Empty
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Introduction to Embedded Microcomputer Systems Lecture 19.2 Jonathan W. Valvano What are interrupts? An interrupt is the automatic transfer of software execution in response to hardware that is asynchronous with current software execution. external I/O device (like a keyboard or printer) or an internal event (like an op code fault, or a periodic timer.) occurs the hardware needs service (busy to done state transition) A thread is defined as the path of action of software as it executes. a background thread interrupt service routine is called. a new background thread is created for each interrupt request. local variables and registers used in the interrupt service routine are unique threads share globals Each potential interrupt source has a separate arm bit. E.g., C0I Set arm bits for those devices from which it wishes to accept interrupts, Deactivate arm bits in those devices from which interrupts are not allowed Each potential interrupt source has a separate flag bit. E.g., C0F hardware sets the flag when it wishes to request an interrupt software clears the flag in ISR to signify it is processing the request Interrupt enable bit, I, which is in the condition code register. enable all armed interrupts by setting I=0, or
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aLec19_timer_threads - Introduction to Embedded...

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