Introduction to Embedded Microcomputer Systems Lecture 5.1 Jonathan W. Valvano Recap 9S12 Architecture, registers Execution thinking about simplified bus cycles Memory map: I/O, RAM, EEPROM Overview Continuation of execution Stack Subroutines Parallel port, direction registers Start with first question of Worksheet 5 Question 1. What are the six phases of execution? 2.4. Simplified 9S12 Machine Language Execution Figure 2.6. Block diagram of a simplified 9S12 computer. The bus interface unit(BIU) •reads data from the bus during a read cycle, •writes data onto the bus during a write cycle. •always drives the address bus and the control signals •effective address register(EAR) contains the data address The control unit(CU) (EE306, EE360M, EE360N)•orchestrates the sequence of operations •issues commands to ALU, BIU •instruction register(IR) contains the op code The registers •high-speed storage devices located in the processor •do not have addresses like regular memory •specific functions explicitly defined by the instruction •Accumulatorscontain data (A, B, D) •Index registerscontain addresses (X, Y) •Program counter(PC) points to instruction to execute next •Stack pointer(SP) points to the top element on the stack context switch when calling and returning from a function pass parameters save temporary information implement local variables •Condition code register(CCR) the status of the previous operation The arithmetic logic unit (ALU) •Arithmetic operations Addition Subtraction Multiplication Division •Logic operations And Or Exclusive or Shift BusMemoryI/OportsAddressDataR/W9S12RegistersControl unitALUBusinterfaceunitProcessorIRPCEARA168
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