DIC_Lecture5_Combinational_Logic_415804626

DIC_Lecture5_Combinational_Logic_415804626 - Combinational...

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Unformatted text preview: Combinational Logic Circuits eibo LIU( 雷波 Leibo LIU( 刘雷波 ) Division of IC & System Design, IMETU ulb@tsinghua.edu.cn liulb@tsinghua.edu.cn Oct. 21, 2010 Key Points Review of Last Lecture — Load Cap. • Propagation delay of CMOS inverter is determined by the time it takes to charge or discharge the load capacitor C L through the PMOS and NMOS transistor C L V DD V DD • Parasitic capacitance C L of the cascaded inverter pair 9 Gate-Drain Cap: C d 2 M 2 M 4 C b2 C 4 gd 12 9 Diffusion Cap: C db 1 , C db 2 9 Gate Cap of Fanout: V in V out1 V out2 db2 C gd12 g4 C g 3 , C g 4 9 Wiring Cap: C W M 1 M 3 C db1 C w C g3 Oct. 21, 2010 2 The CMOS Inverter Key Points Review of Last Lecture – Propagation Delay t =f (R ,C ) = 0.69R C • Switch Model V DD pHL on L on L = V eq dV V R DD 1 ( ) ⎟ ⎞ ⎜ ⎛ − ≈ ⎟ ⎞ ⎜ ⎛ − ≈ + ∫ D DD D DD V DSAT DD V V V V V I V DD λ λ λ 5 1 3 7 1 3 1 2 / 2 / V out ⎠ ⎝ ⎠ ⎝ DSAT DSAT I I 6 4 9 4 where: 2 R on C L ( ) ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − − = 2 DSAT DSAT T DD ' DSAT V V V V L W k I t i V in = V DD ⎟ ⎟ ⎞ ⎜ ⎜ ⎛ + = + = 69 eqp eqn L pLH pHL p R R C . t t t Propagation delay: Oct. 21, 2010 3 The CMOS Inverter ⎟ ⎠ ⎜ ⎝ 2 2 Key Points Review of Last Lecture – Propagation Delay • Current Source 9 NMOS transistor, when discharging capacitor, can be simplified into a current source D ( ) ( ) v DD L v swing L pHL I V C I V C t 2 2 / / = = V DD av av 9 I av , the discharging current, is simply the average value of the currents at the end points of the ansition ( nd ) transition ( V out = V DD and V out = V DD /2) : ( ) ( ) ( ) + + + 2 1 1 DD Dsat DD Dsat V I V I λ λ / V out ⎟ ⎞ ⎜ ⎛ + = 3 1 2 DD Dsat av V I I λ C L I av ⎠ ⎝ 4 ⎞ ⎛ + = 3 1 2 DD sat DD L pHL V I V C t λ V = V D Oct. 21, 2010 4 The CMOS Inverter ⎟ ⎠ ⎜ ⎝ 4 Dsat in DD Key Points Review of Last Lecture – Sizing of Inverter Chain • Sizing of the Inverter Chain In Out C L 1 2 N 9 If N is fixed , therefore : ) 1 ( , γ / N p p N F Nt t F f + = = 9 Otherwise : , ln , ) / 1 ( γ F N e f f = ≈ + ) 1 ( ln ln γ / f t F t f p p + = ¡ γ is determined by technology and normally set to be 1 for most submicron processes ¡ f is normally chosen to be 4. Oct. 21, 2010 5 The CMOS Inverter ln f p p Key Points Review of Last Lecture – Power Dissipation • Power dissipation of CMOS inverter is attributable to 3 parts ¾ 1) Dynamic Power P dyn ue to charging and discharging capacitances 9 Due to charging and discharging capacitances ¾ 2) Direct-Path Currents Power P dp 9 Due to direct conducting between V DD and GND for a short period of time during inverter switching ¾ 3) Static Power P stat 9 Due to the leakage current (current flowing between the supply rails in the absence of switching activity) Total Power Dissipation : P tot = P dyn + P dp + P stat Oct. 21, 2010 6 The CMOS Inverter Key Points Review of Last Lecture – V DD Minimization • Until f reaches F 0.5 , it is allowed to...
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This note was uploaded on 03/28/2011 for the course EE 40260173 taught by Professor Lieboliu during the Spring '11 term at Tsinghua University.

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DIC_Lecture5_Combinational_Logic_415804626 - Combinational...

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