DIC_Lecture6_Combinational_Logic_539507876

DIC_Lecture6_Combinational_Logic_539507876 - Combinational...

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Combinational Logic Circuits eibo LIU( 雷波 Leibo LIU( 刘雷波 ) Division of IC & System Design, IMETU ulb@tsinghua.edu.cn liulb@tsinghua.edu.cn Oct. 28, 2010
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Chapter Outline 1. Introduction 2. Static CMOS Design omplementary CMOS 9 Complementary CMOS 9 Ratioed Logic (Psuedo-NMOS and DCVSL) ass ransistor Logic 9 Pass-Transistor Logic 3. Dynamic CMOS Design 4. Summary 5. Textbook Reference Oct. 28, 2010 2 Combinational Logic Circuits
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2. Static CMOS Design: Ratioed Logic Complementary CMOS 9 Robustness (ratioless logic, full logic swing, high noise margins, symmetrical VTC); 9 No static power consumption (ignoring transient effects during gate switching). 9 The number of transistors required to implement an N-input logic gate is 2 N . Therefore, the area and total capacitance are relatively large. Ratioed Logic 9 Objective: reduce the number of transistors required to implement a iven logic function. given logic function. 9 Approach: consists of an NMOS pull-down network that realizes the logic function, and a simple load device implementing the pull-up n c t i on function. 9 Merits: reduce the number of transistors ( N +1, versus 2 N for complementary CMOS) Oct. 28, 2010 3 Combinational Logic Circuits 9 Demerits: reduce robustness and give rise to extra power dissipation
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2. Static CMOS Design: Ratioed Logic V DD V DD R L Resistive Load PMOS Load F F GND PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 GND GND esistive Load seudo NMOS Resistive Load Pseudo NMOS oal: to reduce the number of devices over complementary CMOS Oct. 28, 2010 4 Combinational Logic Circuits Goal: to reduce the number of devices over complementary CMOS
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2. Static CMOS Design: Ratioed Logic (Pseudo NMOS) Basic Properties of Pseudo NMOS 1 transistors PDN DD OL R V V × = 9 N + 1 transistors 9 V OH = V DD 9 Nominal Low output voltage is not equal to 0 PDN L R R + 9 Decrease noise margins 9 Increase extra static power dissipation. 9 Sizing of the load device relative to the pull-down devices can be used to trade off parameters such as noise margin , propagation delay , as well as power dissipation . ± NM L : need large R L , therefore V OL is low need small therefore small ± t pLH : need small R L , therefore t pLH is small t pLH = 0.69 R L C L Oct. 28, 2010 5 Combinational Logic Circuits
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2. Static CMOS Design: Ratioed Logic (Pseudo NMOS) 2 2 SATp L V Solve for V OL (Assume NMOS resides in linear mode, while PMOS is velocity saturated) ( ) ( ) 0 2 2 = + DSATp DSATp Tp DD p OL OL Tn DD n V V V k V V V V k 9 ssume and =- ( ) p p DSATp Tp DD p W V V V k + μ Assume V OL < V GT , and V Tn V Tp 9 In order to make V OL as small as possible, the PMOS device should be sized much ( ) DSATp n n Tn DD n OL V W V V k V smaller than the NMOS pull-down device. However, this has a negative impact on the propagation delay t pLH .
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This note was uploaded on 03/28/2011 for the course EE 40260173 taught by Professor Lieboliu during the Spring '11 term at Tsinghua University.

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DIC_Lecture6_Combinational_Logic_539507876 - Combinational...

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