DIC_Lecture8_Sequential_Logic_494001242

DIC_Lecture8_Sequential_Logic_494001242 - Sequential Logic...

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Sequential Logic Circuits eibo LIU( 雷波 Leibo LIU( 刘雷波 ) Division of IC & System Design, IMETU [email protected] [email protected] Nov. 18 th , 2010
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Chapter Outline . troduction 1. Introduction 2. Static Latches and Registers 3. Dynamic Latches and Registers ulse Registers 4. Pulse Registers 5. Pipelining 6. Schmitt Trigger ummary 7. Summary 8. Textbook Reference Nov. 18, 2010 2 Sequential Logic Circuits
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1. Introduction: Finite Finite-State Machine State Machine Finite-State Machine Block diagram of a Finite- State Machine, using positive Nov. 18, 2010 3 Sequential Logic Circuits edge-triggered registers
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1. Introduction: Finite Finite-State Machine State Machine ZR36060 Image Other Image A Circle stands for 9 A specific state 9 A series of specific operations Nov. 18, 2010 4 Sequential Logic Circuits FSM Example of ZR36060 JPEG Codec
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1. Introduction: Classification of Memory Elements According to the storage mechanisms harged Positive Feedback Charged Based Static Memory Dynamic Memory 9 State can be preserved as long as the 9 Capacitors have to be refreshed power is turned on 9 Not sensitive to disturbance periodically to compensate the charge leakage 9 Faster and consuming less area Nov. 18, 2010 5 Sequential Logic Circuits 9 Slower and more area-consuming
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1. Introduction: Classification of Memory Elements According to the memory location in the system Foreground Memory (Embedded Into the Logic) 9 Individual Register, Register File/Bank 9 Individual Latch, Latch File/Bank Background Memory (Large Scale, Higher Density) 9 Embedded ROM, RAM, Flash 9 Stand alone ROM, RAM, Flash Nov. 18, 2010 6 Sequential Logic Circuits
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1. Introduction: Classification of Memory Elements Classification of Foreground Memory: Latch and Register Nov. 18, 2010 7 Sequential Logic Circuits
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1. Introduction: Timing Metrics t setup = Setup Time: the time data input must be valid before the clock edge t old = Hold Time: the time data input must be stable after the clock edge hold t clk-q = Worst Case Propagation Delay: the max time that D input is copied to Q output with reference to the clock edge (usually called Propagation Delay ). t cdreg = Best Case Propagation Delay: the min time that D input is copied to the Q output with reference to the clock edge (usually called Contamination Delay ). t clk-q Nov. 18, 2010 8 Sequential Logic Circuits t cdreg
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Look into different time points: t 1 and t 2 Nov. 18, 2010 9 Sequential Logic Circuits setup comb p q clk t t t T + + (max) , Clock period should satisfy :
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Only observe the time points t 1 cdlogic cdreg hold t t t + t hold of FF2 should satisfy : ontamination Delay or Minimum Delay Nov. 18, 2010 10 Sequential Logic Circuits t cd : Contamination Delay or Minimum Delay
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1. Introduction: Timing Metrics Example Expected Clock Period: 2.5 ns Nov. 18, 2010 11 Sequential Logic Circuits
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Static Timing Analysis Results. Obtained from Synopsys Astro. Refer to the previous slide.
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This note was uploaded on 03/28/2011 for the course EE 40260173 taught by Professor Lieboliu during the Spring '11 term at Tsinghua University.

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DIC_Lecture8_Sequential_Logic_494001242 - Sequential Logic...

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