DIC_Lecture11_Wire_23508927

DIC_Lecture11_Wire_23508927 - The Wire Leibo LIU() LIU(...

Info iconThis preview shows pages 1–13. Sign up to view the full content.

View Full Document Right Arrow Icon
The Wire eibo LIU( 雷波 Leibo LIU( 刘雷波 ) Division of IC & System Design, IMETU [email protected] [email protected] Dec. 16, 2010
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Chapter Outline . troduction 1. Introduction 2. Capacitance 3. Resistance lectrical Wire Models 4. Electrical Wire Models 5. Summary 6. Textbook Reference Dec. 16, 2010 2 The Wire
Background image of page 2
1. Introduction : Three Major Interconnection Layers Layers used to realize interconnection in state-of –the-art MOS IC 9 Upper layer : multiple layers of aluminum or copper 9 Middle layer : at least one layer of polysilicon 9 Lower layer : heavily doped n + or p + diffusion layer, which is typically used for the realization of source nd drain regions and drain regions. Dec. 16, 2010 3 The Wire
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
1. Introduction: Wire Examples 0.35 um High End Microprocessor 0.1 um High End Microprocessor Dec. 16, 2010 4 The Wire
Background image of page 4
1. Introduction: The Wire These wires belong to the same layer Transmitters Receiver Schematic View Physical view Dec. 16, 2010 5 The Wire Schematic and physical views of wiring of bus network
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
1. Introduction: Wire Models Wire models for the circuit of previous slide Dec. 16, 2010 6 The Wire All-inclusive Model Capacitance only models
Background image of page 6
1. Introduction : Interconnect Parasitics Interconnect parasitics 9 Cause an increase in propagation delay, or, equivalently, a drop in performance ave an impact on the energy dissipation and the 9 Have an impact on the energy dissipation and the power distribution ause the introduction of extra noise sources which 9 Cause the introduction of extra noise sources, which affect the reliability of the circuit lasses of parasitics Classes of parasitics 9 Capacitive 9 Resistive 9 Inductive Dec. 16, 2010 7 The Wire
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Chapter Outline . troduction 1. Introduction 2. Capacitance 3. Resistance lectrical Wire Models 4. Electrical Wire Models 5. Summary 6. Textbook Reference Dec. 16, 2010 8 The Wire
Background image of page 8
2. Capacitance: Capacitance of Wire Interconnect V D V D Parasitic capacitance C L of the cascaded inverter pair DD DD M 2 M 4 V in V out V out2 C db2 C gd12 C g4 M 1 M 3 C db1 C w C g3 Interconnect Simplified Model Driver Fan-out C L Dec. 16, 2010 9 The Wire
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2. Capacitance: Capacitance Model Parallel-plate W >> t ox 9 Exploiting parallel-plate Cap. model, the wire Cap. can be WL C ox ε = Current flow expressed as: L W t ox Electric ± t ox and ox stand for the thickness and permitivity of the dielectric yer H field 9 Scaling behavior layer. t ox SiO 2 bstrate W t ox Æ 1/S /S substrate L wire S S S = = / 1 L Æ 1/S L Parallel-plate capacitance model of Dec. 16, 2010 10 The Wire L S S × / 1 / 1 , interconnect wire
Background image of page 10
2. Capacitance: Capacitance Model Permittivity: ε ox = ε r 0 Dec. 16, 2010 11 The Wire
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2. Capacitance: Fringing Capacitance With device dimensions scaling down 9 To minimize the resistance of the wires, it is desirable to keep the cross section ( W x H ) of the wire as rge as possible large as possible 9 Small value of W leads to denser wiring and less area overhead Witnessing a steady reduction in the W / H ratio (even below unity) Intel 0.25um interconnect t Fringing - Fringing P-P Fringing Inter- wire P-P Dec. 16, 2010 12 The Wire Fringing Cap.
Background image of page 12
Image of page 13
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/28/2011 for the course EE 40260173 taught by Professor Lieboliu during the Spring '11 term at Tsinghua University.

Page1 / 45

DIC_Lecture11_Wire_23508927 - The Wire Leibo LIU() LIU(...

This preview shows document pages 1 - 13. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online