DIC_Lecture13_Coping_with_Interconnect_424209445

DIC_Lecture13_Coping_with_Interconnect_424209445 - Coping...

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oping with Interconnect Coping with Interconnect eibo IU( 雷波 Leibo LIU( 刘雷波 ) Division of IC & System Design, IMETU ulb@tsinghua.edu.cn liulb@tsinghua.edu.cn Dec. 23, 2010
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Chapter Outline . troduction 1. Introduction 2. Capacitive Parasitics 3. Resistive Parasitics ummary 4. Summary 5. Textbook Reference Dec. 23, 2010 2 Coping with Interconnect
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1. Introduction: Global Overview Dec. 23, 2010 3 Coping with Interconnect
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Chapter Outline . troduction 1. Introduction 2. Capacitive Parasitics 3. Resistive Parasitics ummary 4. Summary 5. Textbook Reference Dec. 23, 2010 4 Coping with Interconnect
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2. Capacitive Parasitics: Reliability and Reliability and Crosstalk Crosstalk X 9 C Y :Cap. between node Y and GND Y V X C XY Floating ines 9 C XY :Parasitic Cap. between node X and Y 9 V X :Voltage step change on node X C Y Lines 9 V :Voltage disturbance on node Y apacitive coupling to a floating line Capacitive coupling to a floating line Circuits susceptive to crosstalk 9 Dynamic network circuits , especially the networks with low swing precharged nodes, located in adjacency to full-swing wires Dec. 23, 2010 5 Coping with Interconnect
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2. Capacitive Parasitics: Reliability and Reliability and Crosstalk Crosstalk Example of crosstalk at dynamic nodes 9 C : Cap. between node Y and GND, C XY V DD CLK Y assume C Y = 6 fF 9 C XY : Cap. between node Y and X C Y In Y 9 Line X is implemented by AL 1 9 Line Y is implemented by polysilicon PDN 1 In 2 In 3 X 2.5 V V 9 Overlap between AL 1 and polysilicon is 3x1 um 2 CLK 0 V 9 Suppose that node Y is precharged to 2.5 V and signal X undergoes a transition from 2.5 V to 0 V. Calculate the voltage drop V Y caused by charge redistribution on node Y . xample 9 1 in P f textbook Dec. 23, 2010 6 Coping with Interconnect Example 9.1 in P 447 of textbook
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2. Capacitive Parasitics: Reliability and Reliability and Crosstalk Crosstalk P-P Cap. Table 4-2 in P 143 of Textbook Example of crosstalk at ynamic nodes V DD ) / 057 . 0 ( ) 1 3 ( 2 2 m fF m C XY μ × × = / 054 . 0 3 2 m m × dynamic nodes C XY CLK Y Fringing Cap. ) ( ) ( f fF 5 . 0 = C Y PDN In 1 In 2 In 3 X 2.5 V V C C C Y XY X XY ) 5 . 2 ( × + = Δ CLK 0 V V V 19 . 0 ) 5 . 2 ( 5 . 0 6 5 . 0 = × + = Keepers needed in dynamic circuitry to come to the “driven situation” … Dec. 23, 2010 7 Coping with Interconnect
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Table 4 Table 4-3 in Chapter 4, P 3 in Chapter 4, P 143 Field Active Poly AL1 AL2 AL3 AL4 AL5 Poly 88 54 Red upper layer Blue Lower layer AL1 30 41 57 40 47 54 3 5 7 6 Shadowless: P-P Cap. (aF/um 2 ) Shadowed : fringing Cap. (aF/um) AL2 13 15 17 36 25 27 29 45 .9 . 41 0 15 41 both sides should be considered AL3 8.9 9. 5 18 19 20 27 49 L4 6.5 6.8 7.0 8.9 15 35 AL4 14 15 15 18 27 45 L5 5.2 5.4 5.4 6.6 9.1 14 38 Dec. 23, 2010 8 Coping with Interconnect AL5 12 12 12 14 19 27 52
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2. Capacitive Parasitics: Reliability and Reliability and Crosstalk Crosstalk Driven line with interferer X 0.5 0.45 4 Vol. (V) t r =5ps X R Y C XY 0.4 0.35 0.3 t r =100ps t r =200ps Y V X C Y 0.25 0.2 0.15 t r =500ps V (Volt) R Y Resistance of the driver 0.1 0.05 0 Voltage response for different rise times of t .5 V) 0 1 0.8 0.6 t (ns) 0.4 0.2 9 Time constant: τ XY = R (C XY + C Y ) V x (0 to 2.5 V) ( R = 10 K Ω C = 20 fF C XY = 5 fF onclusion one: Keep time
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DIC_Lecture13_Coping_with_Interconnect_424209445 - Coping...

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