240ln09 - CURRENT MIRRORS Biasing in integrated circuits is...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 CURRENT MIRRORS LN #9 Biasing in integrated circuits is based upon the use of constant current sources. An effective way to generate an integrated constant current source is with the “Current Mirror” circuit. I o v o -V EE Q2 Q1 I REF BJT Current Mirror Assumptions •Q1 and Q2 are identical •Q2 is maintained in the active region to ensure high β •V EE is not important as long as Q2 is active Q1 and Q2 have equal V BE and thus I E and β is large but finite 1 1 2 1 1 2 1 2 1 >> + = + = + + = + = β for I I I I and I I REF o E REF E o Another non-ideality : the dependence of I o upon V o r this is due to the finite output o of Q2 Since r o is determined by the Early Voltage V A , then if you include the early voltage , the output current in terms of the I REF is + + + A BE EE o REF o V V V V I I 1 2 1 There is also the possibility of mismatched transistors, in the sense that the areas of the base or the doping or the diffusion constants may be slightly different resulting in slightly different I s1 and I s2 . When this is included the expression for I o ( ) / / 1 1 2 1 c c REF I I I = + is modified by using the relation to be
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 I out =I c2 -V A I c1 (I s2 /I s1 ) V CE1 V out =V CE2 ( ) 22 1 21 11 1 1/ 1 ss o c REF II I β   = = +  + If you then include the finite r o of Q2 together with mismatch you have 2 1 1 1 s CE CE REF sA o I VV I IV I + = + + Since the ideal gain (that means the gain that is independent of any load placed upon the output current source) is I s2 /I s2 where gain simply refers to the ratio of the current source produced to the reference current, then in describing the gain that is realized with the load in place we define the parameter called the systematic gain error ε as ( ) ( ) ε 1 2 1 2 1 2 1 2 / 1 1 / 1 1 1 s s A CE CE s s A CE CE I I V V V I I V V V + + + + =
Background image of page 2
3 MOS Current Mirror I o =I D2 v o -V SS M2 M1 I IN + - + - - V in ( ) ( ) ( ) ( ) ( ) ( ) ( ) fixed is L and ratioed is W I L W L W I L W L W I or identical I I I I V V V L W k I V V L W k I V V L W k I V V V IN D o IN D D o ov ov ov D t GS D t GS D t GS ov _ _ _ _ _ __ / / / / / ' 2 / ' 2 / ' 2 1 2 1 1 2 1 2 1 2 1 1 1 2 2 2 2 2 2 2 > = = > −− > −− = = = > −− = = > −− if + = = + = = = Now include finite r o2 ( ) ( ) + = A DS DS IN o V V V I L W L W I 1 2 1 2 1 / / , then So the systematic gain error A DS DS V V V 2 2 = ε For simple MOS , V IN =V GS1 =V t + V ov1 = V t + V ov ( ) region active in remain to L W k I V o o _ _ _ _ / ' 2 2 (min) = (Note V o(min) 3V T in weak inversion) There are various methods/designs to improve the current mirror parameters
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 I o v o -V EE Q2 Q1 R I E 1 + β E I 1 + E I 1 2 + E I ( ) 2 1 2 + E I Assumption: Devices are the same ( ) 2 2 2 1 1 2 1 1 + + + = REF o I I The 1/ β 2 dependence makes I O I REF so R V V V I BE BE CC REF 3 1 = The output resistance R o is due to the resistance of Q2 The output resistance for this circuit has not been improved yet. Remember , an ideal current source should have an infinite R o . So the challenge is to increase R
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/29/2011 for the course ECE 4201 taught by Professor N/a during the Spring '11 term at UConn.

Page1 / 14

240ln09 - CURRENT MIRRORS Biasing in integrated circuits is...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online