divider_phasenoise

divider_phasenoise - IEEE JOURNAL OF SOLID-STATE CIRCUITS,...

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Unformatted text preview: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 775 Phase Noise in Digital Frequency Dividers Salvatore Levantino , Member, IEEE , Luca Roman, Stefano Pellerano, Carlo Samori , Member, IEEE , and Andrea L. Lacaita , Senior Member, IEEE Abstract This paper presents a physical derivation of phase noise in source-coupled-logic frequency dividers. This analysis takes into account both white and flicker noise sources and is verified on two 32/33 dual-modulus prescalers integrated in a 0.35- m CMOS process. Design techniques for high-speed and low-noise operation are provided. The two integrated prescalers are identical apart from a synchronizing flip-flop at the output of one of them. The measured phase spectra are in good agreement with the estimates and demonstrate that the final synchronization allows a better trade-off between noise and power consumption. The maximum operating frequency is 3 GHz, the power consump- tion is 27 mW and the phase noise floor is 163 dBc/Hz referred to the 78-MHz output. Index Terms CMOS integrated circuit, frequency dividers, fre- quency synthesizer, jitter, phase noise, phase-locked loops (PLLs). I. INTRODUCTION A PHASE-LOCKED LOOP (PLL) is used routinely as a variable frequency source in modern radio transceivers. A digital frequency divider is employed within the loop to reduce the reference frequency and to provide the programmability of the synthesizer. The phase noise generated by the divider can affect the synthesizer noise performance within the PLL band, especially if a high division factor is used. In fact, the divider noise power is multiplied by the square of the division factor, when it is transferred to the PLL output. The evaluation of the divider noise is particularly significant in the design of synthesizers for Wireless Local Area Network (WLAN) standards using the Orthogonal Frequency Division Multiplexing (OFDM). In those standards, the signal-to-noise ratio (SNR) can be heavily degraded by the integral phase noise of the frequency synthesizer [1]. Moreover, the PLL for such ap- plications typically employ the integer- architecture, thus fea- turing a high division factor. Therefore, the PLL in-band phase noise can represent the dominant term of the integral value and has to be predicted during the design process. However, the estimation of the divider noise is not straight- forward. The various noise sources in the circuit affect the zero- crossing instants of the output signal and the resultant phase noise is a random process sampled at the divider output fre- quency. For this reason, only time-domain simulations can pre- Manuscript received July 30, 2003; revised November 4, 2003. This work was supported in part by STMicroelectronics, TPA division, Catania, Italy, and by MIUR in the framework of the Italian national project FIRB under Contract RBNE01F582....
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divider_phasenoise - IEEE JOURNAL OF SOLID-STATE CIRCUITS,...

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