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ECE264D_MIDTERM_solution

ECE264D_MIDTERM_solution - UCSD ECE264D MIDTERM EXAM Nov...

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UCSD ECE264D MIDTERM EXAM, Nov 5 th , FALL 2009 Instructor: Dr. Gang Zhang Student Name:____________________________________ PID#_______________________________________ 1. Below is a dual-modulus divider with inputs: Modulus control (MC) and clock (CK), output: Q0. Q1: what are the division ration when MC=0 and MC=1; Q2: draw timing diagram and state table when MC=1, assume DFF Q’s initially are set to 1’s Q3: what is the max working clock frequency when MC=1, assume “ and t ” is and delay, “ dff t ” is DFF clock to output delay, “ setup t ” is DFF setup time (data needs to be available to setup t before clock rising edge to avoid error/metastability). Q1 Solution: MC=1: { n n n n n n n n Q Q Q Q Q Q Q Q 2 1 0 2 1 1 1 2 1 1 1 = = = + + + Q2 Solution: Q3 Solution: For any of critical paths, we have setup nand dff ck t t t T + + setup nand dff ck t t t f + + = 1 max
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2. A type II PLL with block gains specified as below. There are three noisy buffers at different locations. Q1: derive phase noise transfer functions for each buffer: from the buffers to Fout: Q2; are they high pass? Low pass? Or all pass?
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