ECE264D_Project2

ECE264D_Project2 - Design of CMOS RF Frequency Synthesizers...

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Design of CMOS RF Frequency Synthesizers Project 2: Design of a Frac-N ADPLL through Behavioral modeling GANG ZHANG September 2009 © 2009 G. Zhang ECE264D Fall 2009
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s Time-domain behavioral modeling is critical in PLL design s Critical to understanding nonlinear, discrete-time system: acquisition transient, spurs, quantization in ADPLL etc.; small-signal linear model is not adequate; s Critical to system performance verification. s Spice-like simulation tools cannot handle these tasks s System too large to simulate: large scale digital and analog/RF; s Extreme time constants: DCO dithering in pS, loop time-constant in mS; s Solution: time-domain behavioral modeling Time Domain Behavioral Modeling of PLL Page 2 s Can be done with Matlab or VerilogA, VHDL; s Benefits from this project: s Deeper understanding of PLL system dynamics: frequency to phase conversion, DSM divider dithering, acquisition, locking behaviors etc. s Understanding of ADPLL system: time quantization, digital controlled oscillator; s A much more direct exposure to a working ADPLL system; s Sounds like an overwhelming task. . s Can be accomplished by decomposing the system to sub-blocks: divide and conquer s And with Team Work. ECE264D RF Frequency Synthesizers © 2009 G. Zhang
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Phase-to-Digital Converter ADPLL under investigation PDC Digital loop filter DCO N/N+1 Vrf Ndiv output digital fref analog DT CT Page 3 s Very much like analog frac-N PLL with s PFD charge pump b phase to digital converter (PDC); s VCO b DCO; s RC loop filter b digital filter; s Actually simpler to model than analog counterpart in many aspects; ECE264D RF Frequency Synthesizers © 2009 G. Zhang DSM
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ECE264D_Project2 - Design of CMOS RF Frequency Synthesizers...

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