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hw1 - Synthesizers © 2009 G Zhang-70dBc spur-120dBc/Hz...

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! A LO with phase noise of -120dBc/Hz at 1MHz offset from the carrier, assume - 120dBc/Hz phase noise is uniform within 100kHz bandwidth. There is a jammer at 1MHz offset,+65dB relative to signal power(at carrier frequency). ! Question 1: after direct down conversion, how much is the down converted jammer power relative to the signal (within 100kHz base-band signal band-width); ! Question 2: in order to make the down converted jammer to be 10dB below signal, what is the max allowed phase noise at 1MHz offset; ! Question 3: if in addition to -120dBc/Hz phase noise (as in Question 1), there is also a spur at 1MHz offset with power of -70dBc, what is the down converted total jammer ECE264D Homework1, Prob#1 Page 1 power relative to signal (in 100kHz band, assume two parts of down-converted jammer power are uncorrelated). ECE264D RF Frequency
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Unformatted text preview: Synthesizers © 2009 G. Zhang-70dBc spur-120dBc/Hz Q1,Q2 Q3 1MHz 65dB signal jammer ! A PLL with two forward charge-pump/loop filter paths as shown below, assume small signal linear model; ! Question1: derive the open loop transfer function, find poles and zeros; ! Question2: sketch the Bode’s plot of loop transfer: magnitude and phase (estimate with reasoning is fine, no need to be exact, assume C1 is much bigger than C2); ! Questions 3:generally C1 is too big to be integrated on chip, is there a way to reduce C1 by 10x, without changing PLL loop transfer function/bandwidth (hint, Icp1, Icp2 don’t have to be the same)? ECE264D homework1, Prob#2 UP Icp1 C1 Page 2 ECE264D RF Frequency Synthesizers © 2009 G. Zhang PFD UP/DN DN Icp1 UP DN Icp2 Icp2 + VCO Kv ideal voltage adder C2 R1 fref Div by N...
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hw1 - Synthesizers © 2009 G Zhang-70dBc spur-120dBc/Hz...

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