This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: Synthesizers 2009 G. Zhang-70dBc spur-120dBc/Hz Q1,Q2 Q3 1MHz 65dB signal jammer ! A PLL with two forward charge-pump/loop filter paths as shown below, assume small signal linear model; ! Question1: derive the open loop transfer function, find poles and zeros; ! Question2: sketch the Bodes plot of loop transfer: magnitude and phase (estimate with reasoning is fine, no need to be exact, assume C1 is much bigger than C2); ! Questions 3:generally C1 is too big to be integrated on chip, is there a way to reduce C1 by 10x, without changing PLL loop transfer function/bandwidth (hint, Icp1, Icp2 dont have to be the same)? ECE264D homework1, Prob#2 UP Icp1 C1 Page 2 ECE264D RF Frequency Synthesizers 2009 G. Zhang PFD UP/DN DN Icp1 UP DN Icp2 Icp2 + VCO Kv ideal voltage adder C2 R1 fref Div by N...
View Full Document
This note was uploaded on 04/02/2011 for the course ECE 264 taught by Professor Song during the Spring '11 term at UCSB.
- Spring '11