hw2 - ECE264D Homework2, Prob#1 ! ! ! Q1: Plot the timing...

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! Q1: Plot the timing diagram of the following programmable counter: set input as in6-in1 to 001111b (div15), plot waveforms on relevant nodes, RELOAD is the final output; ! Q2: estimate the delay from the corresponding triggering CLK rising edge to the rising edge of D0 (in terms of logic block delays, D0 is retimed by FF0 to generate the final output RELOAD); ! Q3: Qualitatively estimate the max CLK frequency for this divider to work properly (only consider div15 case, in terms of logic block delays, give reasoning); ECE264D Homework2, Prob#1 Page 1 ECE264D RF Frequency Synthesizers © 2009 G. Zhang
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! For a type II PLL with a 3 rd order loop filter, assume small signal continuous time linear model, if division ratio N=200, Icp=200uA, VCO Kv=100MHz/V, keep C1/C2=16, ! Q1: to achieve about 20kHz closed loop -3dB bandwidth, at the same time achieve good phase margin (>50 degrees), what are the values for R1 and C1 (estimate based on Bode plot of loop transfer, give reasoning); ! Q2: what is your estimated phase margin achieved in Q1? ! Q3: if Kv changes to 50MHz/V when the PLL locks to a different frequency, with all other
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This note was uploaded on 04/02/2011 for the course ECE 264 taught by Professor Song during the Spring '11 term at UCSB.

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hw2 - ECE264D Homework2, Prob#1 ! ! ! Q1: Plot the timing...

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