hw2_sol_v0

# hw2_sol_v0 - o p z H 56 tan tan 1 1 ≅-=-ANSWER out s f...

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Delay=1 x DFF + 1 x NAND1 + 1 NOR Answer: The critical path for this divider maybe one of the following: Case1: Path associated with the generation of D0: 0 3 1 1 ff setup NOR NAND dff clk t t t t T + + + 0 3 1 1 max 1 ff setup NOR NAND dff t t t t f + + + = Case2: Path associated with Reload signal & input reload logic 1 0 } , max{ dff or and INV dff clk t t t t t T + + + 1 0 max } , max{ 1 dff or and INV dff t t t t t f + + + = Most probably the second path will be the critical one as the RELOAD signal has to drive a large (many AND & OR gates).
ANSWER: ) / 1 ( ( / 1 1 1 1 2 1 z 1 1 2 p LPF s C C s s sC R sC Z ω + + + = + + = where 1 1 1 R C z = 1 2 1 2 1 2 1 1 R C R C C C C p + = N s K s C C s s I A V p cp 1 2 ) / 1 ( ( / 1 2 2 1 z + + + = π β Phase Margin: p z H φ 0 1 0 1 tan tan - - - = when z p C C 16 16 2 1 = = Maximize Phase Margin z p H d d = = 0 0 0 20 2 4 1 4 0 × = = = p z krad/sec = 1 | @ | 0 A 1 ) ( 1 ) ( 1 ) ( 1 2 2 2 1 2 2 0 2 0 0 = + + + C C N I K p z cp v pF C nF C 240 , 84 . 3 2 1 = = (need further verification) Ω = = k R C R z 28 . 8 1 1 1 1 Phase Margin= o p z H 62 tan tan 0 1 0 1 - = - - ANSWER: v v K K 2 1 ' = A 6 dB lower than original one. Phase Margin=

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Unformatted text preview: o p z H 56 tan tan ' 1 ' 1 ≅-=--ANSWER: out s f MHz f = = 10 Q & Q flicker corner=100 KHz ⇒ flicker corner frequency < 2 s f No overlap for flicker noise. Phase Noise = 16 13 10 94 . 3 10 97 . 1--× + × m f ANSWER: for flicker noise (no folding) 100 1 2 × ⇒ ∞ noise F out i.e 20 dB improvement For white noise (folding) 10 1 × ⇒ ∞ noise F out i.e. 10 dB improvement...
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hw2_sol_v0 - o p z H 56 tan tan 1 1 ≅-=-ANSWER out s f...

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